SPRZ455D december 2020 – june 2023 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
ADVANCE INFORMATION
C71x: VCOP Aliasing for CPU Loads and Stores Is Not Supported for Non-Aligned Accesses to the Last Line in the IBUF Buffers
The C71x memory system supports EVE-style VCOP aliasing for CPU loads and stores, in addition to DMAs and accesses made through the streaming engine. When this aliasing is enabled, non-aligned loads and stores to the last line (128 bytes) in the IBUF buffers may not get aliased in some configurations.
Table 3-1 shows the actual behavior.
| CPU Aliasing ON | |||||
|---|---|---|---|---|---|
| IBUFLA | IBUFHA | IBUFLB | IBUFHB | L1D Action | |
| Owned | CPU | CPU | DMA | DMA | No issue |
| DMA | DMA | CPU | CPU | No issue | |
| DMA | CPU | CPU | DMA | See (1) | |
| CPU | DMA | CPU | DMA | See (2) | |
The IBUF buffers should be sized such that the last lines (128 bytes) for all the four buffers are not used.