Details

The 2-L SerDes PCIe Reference Clock Output will be temporarily disabled when either of the following occur:

• Scenario A: Changing Data Rates to or from 8.0 GT/s, because the SerDes Common PLL is reprogrammed during the speed change
• Scenario B: Changing Data Rates to or from any speed while the second lane of the SerDes is in a reset/powered-down state or used together with the first lane to form a two-lane link.
  • Examples of affected configurations include:
    • PCIe 1L with Second lane in reset/powered-down
    • PCIe 2L
  • Configurations not affected include:
    • PCIe + USB (with USB not in reset/powered-down)
    • PCIe + Ethernet (SGMII/QSGMII/XFI, not in reset/powered-down)

Some external PCIe components that are using the PCIe Reference Clock may not tolerate the disabling of the clock when changing data rates. However, the 2-L and 4-L SerDes in this Device family does not have an issue accepting this Reference Clock behavior. This means that a link that connects the 2-L or 4-L SerDes in one Device to the 2-L or 4-L SerDes in a second Device will not have an issue when one Device generates the Reference Clock and the other Device receives the Reference Clock.

Workaround

One workaround for both Scenario A and Scenario B is to use an external clock source to supply the PCIe Reference Clock to both the Root Complex and End Point Devices of the Link.

Scenario A can also be worked around by either of the following methods:

1. Use a Single Link PCIe configuration in which CMNPLLLC is used for all PCIe data rates (2.5GT/s, 5.0GT/s, and 8.0GT/s). PHY_PLL_CFG[0] should also be set to 1'b0 to prevent reprogramming of CMNPLLLC when changing Data Rates to/from 8.0 GT/s.
2. Do not operate the PCIe interface at the 8.0 GT/s Data Rate

Scenario B can also be worked around by either of the following methods:

1) Ensure that the second lane of the 2-L Serdes is out of reset, not part of a two-lane link, and not in a low-power state when the first lane is going through a speed change. One way to accomplish this is to setup dummy SerDes configurations on unused Lanes.

To setup a dummy Lane for the PCIe 1L configuration:

Setup second lane as USB or Q/SGMII. This can be done by configuring LANE_FUNC_SEL field in CTRLMMR_SERDES*_LN1_CTRL register in CTRL_MMR0 space.

Also SERDES configuration has to be performed for the second lane based on the protocol selected.

Please note that USB or Q/SGMII on second lane is a dummy configuration and is not expected to be functional.

Force enable the second lane by setting P1_FORCE_ENABLE to 1’b1 in LANECTL1 register. P1_ENABLE bit has to be retained at 1’b0.

Please note that if USB is selected for second lane, it is a dummy configuration and USB will not be functional. This is because forcing lane enable is not compatible with USB.

Q/SGMII can also be selected as dummy configuration if application is not using a given Q/SGMII instance. However, in case of Q/SGMII, this does not have to be a dummy configuration and it can be functional if required by application.

To setup dummy Lanes for the PCIe 2L configuration:

Setup a second SERDES to supply reference clock to refclk_p/refclk_n SERDES pins. For example if SERDES0 is being used for PCIe 2L then SERDES1/SERDES2/SERDES3 can be used as the second SERDES.

Select USB or Q/SGMII or PCIe (different instance than one being worked around) to be used on both lanes of the second SERDES using CTRLMMR_SERDES*_LN*_CTRL register. If USB is the selected protocol, second lane has to be marked as “Not used” in this register, but both lanes of SERDES have to be configured for USB.

Also program SERDES as per the selected protocol. Please note that this second SERDES is acting as a dummy configuration and is not expected to be functional. As a result, the SERDES and the Controller instance not used by the application has to be selected.

Force enable both lanes of the SERDES by setting P0_FORCE_ENABLE to 1’b1 in LANECTL0 register and P1_FORCE_ENABLE to 1’b1 in LANECTL1 register. P0_ENABLE and P1_ENABLE bits have to be retained at 1’b0.

Leave REFCLKP and REFCLKN pins of the first SERDES unconnected. Instead use REFCLKP and REFCLKN pins of the second SERDES to supply reference clock to link partner.

Provide same SOC internal reference clock to both first and second SERDES. This is important to ensure that the reference clock going to pins is phase aligned and within jitter limits with respect to the serial pins on the first SERDES.

2) Only operate the PCIe interface at the 2.5 GT/s Data Rate