SPRZ455D december 2020 – june 2023 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
ADVANCE INFORMATION
PCIe: Automatic compliance entry fails when unused SERDES lanes are not assigned to PCIe Controller
PCIe fails to enter compliance state when connected to a passive load. This happens when unused SERDES lanes are not assigned to PCIe Controller. For example, if PCIe is configured in 1 lane mode, then compliance entry fails if only lane 0 of SERDES is assigned to PCIe Controller and lanes 1, 2, and 3 are not assigned to PCIe Controller.
Status signals going from SERDES to PCIe Controller are tied-off when a lane is not assigned to PCIe. Signal indicating electrical idle is incorrectly tied-off to a state that indicates non-idle. As a result, Controller sees unused lanes to be out of electrical idle (indicating that the lane is not connected to passive load) and this prevents compliance entry.
Please note that this issue only affects automatic compliance entry mechanism when connected to passive load (for example a scope that presents termination in its receive lines but does not bring its transmit lines out of electrical idle). This issue does not affect Enter Compliance or Compliance Receive mechanisms defined by PCIe specification.
Only available workaround is to assign all SERDES lanes to PCIe during compliance validation.