SPRZ455D december 2020 – june 2023 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
ADVANCE INFORMATION
C7x SE: SE Can Hang when a 2 dataphase transaction comes back with differing rstatuses
In rare circumstances, such as a particularly located, 2-bit uncorrectable error in memory that occurs within the data being streamed in through SE, a hang can occur within C7x. For this scenario to occur: the uncorrectable error must be the first error (parity or otherwise) that SE encounters; it must have particular alignment within the stream; and SE must be far enough ahead of C7x's consumption of data that SE allocates the line in its tags, then requests and receives the line before having room in its tags/internal structures to allocate the next line; thus, this is extremely unlikely to occur.
In normal use cases where SE is streaming from L2SRAM or MSMCSRAM, a particularly aligned, uncorrectable error is the only way that this bug can be encountered. If SE is used to stream from other endpoints, there are other particularly aligned errors that can cause this, but fetching from such endpoints has a much greater round trip time, so it is more unlikely for SE to be in the state where it can hang at the time of the response carrying the error returns to SE. When the hang occurs, the only way to recover is to fully reset the C7x.
Only action that can be taken is recovery. If C7x hangs, it must be reset.