SPRZ455D december 2020 – june 2023 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
ADVANCE INFORMATION
OSPI: Internal PHY Loopback and Internal Pad Loopback clocking modes with DDR timing inoperable
The OSPI Internal PHY Loopback mode and Internal Pad Loopback mode uses “launch edge as capture edge” (same edge capture, or 0-cycle timing).
The programmable receive delay line (Rx PDL) is used to compensate for the round trip delay (Tx clock to Flash device, Flash clock to output and Flash data to Controller).
In the case of internal and IO loopback modes, the total delay of the Rx PDL is not sufficient to compensate for the round trip delay, and thus these modes cannot be used.
The table below describes the recommended clocking topologies in the OSPI controller. All other modes not described here are affected by the advisory in DDR mode and are not recommended clocking topologies.
| Clocking Mode Terminology | CONFIG_REG.PHY_MODE_ENABLE | READ_DATA_CAPTURE.BYPASS | READ_DATA_CAPTURE.DQS_EN | Board implementation |
|---|---|---|---|---|
| No Loopback, no PHY | 0 (PHY disabled) | 1 (disable adapted loopback clock) | X | None. Relying on internal clock. Max freq 50MHz. |
| External Board Loopback with PHY | 1 (PHY enabled) | 0 (enable adapted loopback clock) | 0 (DQS disabled) | External Board Loopback (OSPI_LOOPBACK_CLK_SEL = 0) |
| DQS with PHY | 1 (PHY enabled) | X (DQS enable has priority) | 1 (DQS enabled) | Memory strobe connected to SOC DQS pin |
None. Please use one of the unaffected clocking modes based on the table in the description