SPRZ457H January 2021 – December 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
PCIe: MSI or MSI-X does not trigger interrupt if address is not aligned to 8-bytes
While operating as Root Complex, PCIe MSI or MSI-X reception causes a write to GIC ITS register space in order to trigger interrupt to CPU cores. If the address used in the MSI or MSI-X transaction is NOT aligned to 8-bytes, the interrupt to CPU cores does not occur.
For example, MSI or MSI-X address with lower bits set to 0x10 does result in an interrupt whereas 0x14 fails.
None available. MSI or MSI-X transaction has to be issued to 8-byte aligned ITS address.