SPRZ458F May   2019  – February 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

 

  1.   1
  2.   TMS320F2838x MCUs Silicon Errata Silicon Revisions A, 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision A Usage Notes and Advisories
    1. 3.1 Silicon Revision A Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 GPIO: GPIO Data Register is Reset by CPU1 Reset Only
      4. 3.1.4 McBSP: XRDY bit can Hold the Not-Ready-Status (0) if New Data is Written to the DX1 Register Without Verifying if the XRDY bit is in its Ready State (1)
      5. 3.1.5 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
    2. 3.2 Silicon Revision A Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4. 3.2.1 Advisory
      5. 3.2.2 Advisory
      6. 3.2.3 Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16.      Advisory
      17.      Advisory
      18.      Advisory
      19.      Advisory
      20.      Advisory
      21.      Advisory
      22.      Advisory
      23.      Advisory
      24.      Advisory
  6. 4Silicon Revision 0 Usage Notes and Advisories
    1. 4.1 Silicon Revision 0 Usage Notes
    2. 4.2 Silicon Revision 0 Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
  7. 5Documentation Support
  8. 6Trademarks
  9. 7Revision History

Advisory

Ethernet: MAC Receive VLAN Tag Hash Filter Always Operates in Default Mode

Revisions Affected

0, A

Details

The ETV, DOVLTC, and ERSVLM bits of the MAC_VLAN_Tag_Data register accessed via the MAC_VLAN_Tag_Ctrl register (Extended Receive VLAN filtering is selected) are used to program the mode of operation of the Receive VLAN Hash Filtering. The ETV bit is used to enable computation of Hash for only 12 bits of VLAN Tag. The DOVLTC bit is used to disable VLAN Type Check for VLAN Hash filtering. The ERSVLM bit is used to enable VLAN Hash filtering for S-VLAN Type. However, due to this defect, the Receive VLAN Hash filter always operates in default mode; that is, VLAN Hash is always computed for 16-bits (ETV = 0) of C-VLAN Tag (DOVLTC = 0 and ERSVLM = 0). Therefore, programming the ETV, DOVLTC, or ERSVLM bits to 1 has no effect because these bits have an incorrect read-only attribute. As a result, unintended packets might be forwarded to the application due to an incorrect filter pass or bypass results/status. Also, packets might be dropped in the MAC due to an incorrect filter fail result.

The defect is applicable when non-default VLAN Hash filtering modes are programmed; that is, one or more of the ETV, DOVLTC, and ERSVLM bits are set to 1.

Workaround

The software should disable the Receive VLAN Hash filtering by setting the VTHM bit of the MAC_VLAN_Tag_Ctrl register to 0 (when non-default VLAN Hash filtering mode is required) and use the alternative filtering methods available in the hardware (perfect or inverse VLAN filtering), or perform filtering in software.

Use only the default VLAN Hash filtering modes.