SPRZ458F May 2019 – February 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
Ethernet: False Dribble and CRC Error Reported in RMII 10Mbps Mode for a Specific Phase Relation Between MAC Receiver Clock and Assertion of RMII CRS_DV Input
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If the MAC is operating in the RMII 10Mbps speed mode and the RMII CRS_DV is asserted two RMII clock rising edges ahead of data, the Ethernet module reports a false dribble and a CRC error in the Receive status. The dribble error is reported when the Ethernet module receives an odd number of nibbles (4-bit words) and a CRC error is additionally reported. There is no data loss or corruption of packets forwarded to the software. However, if the error-packet drop is enabled (FEP bit in MTL_RxQ(#i)_Operation_Mode register is set to 0), the Ethernet module drops the packets, causing packet loss and impacting performance. If the error-packet drop is disabled (FEP bit in MTL_RxQ(#i)_Operation_Mode register is set to 1), the Ethernet module forwards the packet to the software, up to the byte boundary, and there is no data loss or corruption.
If the error-packet drop is enabled (FEP bit in MTL_RxQ(#i)_Operation_Mode register is set to 0), software can disable it and take the dropping decision based on the Rx status. If the error-packet drop is disabled (FEP bit in MTL_RxQ(#i)_Operation_Mode register is set to 1), software can ignore the dribble and CRC error and accept packets that have both these errors together. The occurrence of real dribble error is rare and happens when there are synchronization issues due to faulty clock recovery.