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SPRZ496D October 2021 – May 2024 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1

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TMS320F28003x Real-Time MCUs Silicon ErrataSilicon Revision 0
1Usage Notes and Advisories Matrices
1. 1.1 Usage Notes Matrix
2. 1.2 Advisories Matrix
2Nomenclature, Package Symbolization, and Revision Identification
3Silicon Revision 0 Usage Notes and Advisories
1. 3.1 Silicon Revision 0 Usage Notes
2. 3.2 Silicon Revision 0 Advisories
  1. 3.2.1 Advisory
  2. Advisory
  3. Advisory
  4. 3.2.2 Advisory
  5. Advisory
  6. Advisory
  7. Advisory
  8. Advisory
  9. 3.2.3 Advisory
  10. Advisory
  11. 3.2.4 Advisory
  12. Advisory
  13. Advisory
  14. Advisory
  15. 3.2.5 Advisory
  16. Advisory
  17. 3.2.6 Advisory
  18. 3.2.7 Advisory
  19. Advisory
  20. 3.2.8 Advisory
  21. Advisory
  22. 3.2.9 Advisory
  23. 3.2.10 Advisory
  24. Advisory
  25. Advisory
  26. Advisory
  27. Advisory
4Documentation Support
5Trademarks
6Revision History

Advisory

DCAN: During DCAN FIFO Mode, Received Messages May be Placed Out of Order in the FIFO Buffer

Revision Affected

Details

In DCAN FIFO mode, received messages with the same arbitration and mask IDs are supposed to be placed in the FIFO in the order in which they are received. The CPU then retrieves the received messages from the FIFO via the IF1/IF2 interface registers. Some messages may be placed in the FIFO out of the order in which they were received. If the order of the messages is critical to the application for processing, then this behavior will prevent the proper use of the DCAN FIFO mode.

Workaround

Use the DMA to read out the FIFO via the IF3 register. Each time a message is received into the FIFO, the data is also copied to the IF3 register, and a DMA request Is generated to the DMA module to read out the data.