SPRZ506C October 2022 – May 2024 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137
Memory: Prefetching Beyond Valid Memory
0, A, B, C
The C28x CPU prefetches instructions beyond those currently active in its pipeline. If the prefetch occurs past the end of valid memory, then the CPU may receive an invalid opcode.
M1 – The prefetch queue is 8 x16 words in depth. Therefore, code should not come within 8 words of the end of valid memory. Prefetching across the boundary between two valid memory blocks is all right.
Example 1: M1 ends at address 0x7FF and is not followed by another memory block. Code in M1 should be stored no farther than address 0x7F7. Addresses 0x7F8–0x7FF should not be used for code.
Example 2: M0 ends at address 0x3FF and valid memory (M1) follows it. Code in M0 can be stored up to and including address 0x3FF. Code can also cross into M1, up to and including address 0x7F7.
| MEMORY TYPE | ADDRESSES IMPACTED |
|---|---|
| M1 | 0x0000 07F8–0x0000 07FF |