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SPRZ506C October 2022 – May 2024 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137

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TMS320F28003x Real-Time MCUs Silicon ErrataSilicon Revision 0
1Usage Notes and Advisories Matrices
1. 1.1 Usage Notes Matrix
2. 1.2 Advisories Matrix
2Nomenclature, Package Symbolization, and Revision Identification
3Silicon Revision C Usage Notes and Advisories
1. 3.1 Silicon Revision C Usage Notes
2. 3.2 Silicon Revision C Advisories
  1. Advisory
  2. Advisory
  3. Advisory
  4. Advisory
  5. Advisory
  6. Advisory
  7. Advisory
  8. 3.2.1 Advisory
  9. Advisory
  10. 3.2.2 Advisory
  11. 3.2.3 Advisory
  12. Advisory
  13. Advisory
  14. Advisory
  15. Advisory
  16. 3.2.4 Advisory
  17. Advisory
4Silicon Revision B Usage Notes and Advisories
1. 4.1 Silicon Revision B Usage Notes
2. 4.2 Silicon Revision B Advisories
5Silicon Revision A Usage Notes and Advisories
1. 5.1 Silicon Revision A Usage Notes
2. 5.2 Silicon Revision A Advisories
6Silicon Revision 0 Usage Notes and Advisories
1. 6.1 Silicon Revision 0 Usage Notes
2. 6.2 Silicon Revision 0 Advisories
7Documentation Support
8Trademarks
9Revision History

3.1.2 Caution While Using Nested Interrupts

Revisions Affected: 0, A, B, C

If the user is enabling interrupts using the EINT instruction inside an interrupt service routine (ISR) in order to use the nesting feature, then the user must disable the interrupts before exiting the ISR. Failing to do so may cause undefined behavior of CPU execution.