SPRZ507C January 2023 – July 2024 TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1
- 1
- TMS320F28003x Real-Time MCUs Silicon ErrataSilicon Revision 0
- 1Usage Notes and Advisories Matrices
- 2Nomenclature, Package Symbolization, and Revision Identification
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3Silicon Revision B Usage Notes and Advisories
- 3.1
Silicon Revision B Usage Notes
- 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
- 3.1.2 Caution While Using Nested Interrupts
- 3.1.3 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
- 3.2 Silicon Revision B Advisories
- 3.1
Silicon Revision B Usage Notes
- 4Silicon Revision A Usage Notes and Advisories
- 5Silicon Revision 0 Usage Notes and Advisories
- 6Documentation Support
- 7Trademarks
- 8Revision History
Advisory
CMPSS: A CMPSS Glitch can Occur if Comparator Input Pin has AGPIO Functionality and ADC is Sampling the Input Pin
Revisions Affected
0, A, B
Details
The combinations of use cases for a specific analog input pin that need special considerations are shown in Table 3-2. As shown in this table, special considerations or workarounds need to be used for the combination of CMPSS Input, ADC Sampling, and AGPIO.
| FUNCTION USED ON A SPECIFIC ANALOG PIN | COMPONENT USED | ||||
|---|---|---|---|---|---|
| CMPSS Comparator Input | Yes | - | Yes | - | Yes |
| ADC Sampling | Yes | Yes | - | Yes | Yes |
| AGPIO Analog Pin Type | Yes | Yes | Yes | - | - |
| AIO Analog Pin Type | - | - | - | Yes | Yes |
| Result | Workaround needed | No special analysis or workaround needed | |||
The AGPIO analog pin path contains an extra series switch of 53Ω. This creates a low-capacitance isolated node shared by the ADC and CMPSS comparator, as shown in Figure 3-1. This node can be disturbed when the ADC samples the channel (depending on the prior voltage stored on the ADC sample-and-hold capacitor), and this disturbance can cause a false CMPSS event of up to 50ns. To accommodate this potential disturbance, the workarounds below can be implemented.
Figure 3-1 Analog Subsystem Diagram with
AGPIO and AIO Analog Pin TypesWorkarounds
- Use a different pin (that is AIO pin type) for analog channels that need both ADC and CMPSS together.
- Use the CMPSS Digital Filter with a setting of 50ns or greater, which will filter the temporary disturbance.
- Pre-condition the sample-and-hold capacitor of the ADC so that the disturbance will not cause a false trip. For example, perform a dummy read of a 3.3V connection from a different channel on the ADC immediately before the impacted channel is read, so the disturbance is in the positive direction, away from the false trip. The opposite dummy read of a 0V signal would be used if the false trip is inverted in polarity.