SPRZ507C January   2023  – July 2024 TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1

 

  1.   1
  2.   TMS320F28003x Real-Time MCUs Silicon ErrataSilicon Revision 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision B Usage Notes and Advisories
    1. 3.1 Silicon Revision B Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
    2. 3.2 Silicon Revision B Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7. 3.2.1 Advisory
      8.      Advisory
      9. 3.2.2 Advisory
      10.      Advisory
      11. 3.2.3 Advisory
      12.      Advisory
      13.      Advisory
      14. 3.2.4 Advisory
      15. 3.2.5 Advisory
      16.      Advisory
      17.      Advisory
      18. 3.2.6 Advisory
      19.      Advisory
  6. 4Silicon Revision A Usage Notes and Advisories
    1. 4.1 Silicon Revision A Usage Notes
    2. 4.2 Silicon Revision A Advisories
  7. 5Silicon Revision 0 Usage Notes and Advisories
    1. 5.1 Silicon Revision 0 Usage Notes
    2. 5.2 Silicon Revision 0 Advisories
  8. 6Documentation Support
  9. 7Trademarks
  10. 8Revision History

2.3 Package Symbolization and Revision Identification

Figure 2-1, Figure 2-2, Figure 2-3, Figure 2-4, Figure 2-5, Figure 2-6, Figure 2-7, and Figure 2-8 show the package symbolization. Table 2-1 lists the silicon revision codes.

TMS320F2800157-Q1 TMS320F2800157 Package Symbolization for PN Package Figure 2-1 Package Symbolization for PN Package
TMS320F2800157-Q1 TMS320F2800157 Package Symbolization for PN Package (AEC-Q100 Grade 1 Qualification) Figure 2-2 Package Symbolization for PN Package (AEC-Q100 Grade 1 Qualification)
TMS320F2800157-Q1 TMS320F2800157 Package Symbolization for PM Package Figure 2-3 Package Symbolization for PM Package
TMS320F2800157-Q1 TMS320F2800157 Package Symbolization for PM Package (AEC-Q100 Grade 1 Qualification) Figure 2-4 Package Symbolization for PM Package (AEC-Q100 Grade 1 Qualification)
TMS320F2800157-Q1 TMS320F2800157 Package Symbolization for PHP Package Figure 2-5 Package Symbolization for PHP Package
TMS320F2800157-Q1 TMS320F2800157 Package Symbolization for PHP Package (AEC-Q100 Grade 1 Qualification) Figure 2-6 Package Symbolization for PHP Package (AEC-Q100 Grade 1 Qualification)
TMS320F2800157-Q1 TMS320F2800157 Package Symbolization for PHP Package (AEC-Q100 Grade 0 Qualification) Figure 2-7 Package Symbolization for PHP Package (AEC-Q100 Grade 0 Qualification)
TMS320F2800157-Q1 TMS320F2800157 Package Symbolization for RHB Package (AEC-Q100 Grade 1 Qualification) Figure 2-8 Package Symbolization for RHB Package (AEC-Q100 Grade 1 Qualification)
Table 2-1 Revision Identification
SILICON REVISION CODESILICON REVISIONREVID(1)
Address: 0x5D00C		COMMENTS(2)
Blank00x0000 0001This silicon revision is available as TMX.
A A 0x0000 0002 This silicon revision is available as both TMX and TMS.
B B 0x0000 0003 This silicon revision is available as TMS.
(1) Silicon Revision ID
(2) For orderable device numbers, see the PACKAGING INFORMATION table in the TMS320F280015x Real-Time Microcontrollers data sheet.
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