Details:

A hardware bug is present in the C7120 Streaming Engine top level clock gating logic that can lead to the C7120 CPU hanging.

Hanging can occur regardless of Streaming Engine Programming and can only be avoided by overriding the top level clock gating to prevent Streaming Engine and other C7120 Corepac components from going idle.

Workaround(s):

The DSP_<COREID>_DEBUG_CLKEN_OVERRIDE fields of the COMPUTE_CLUSTER_CFG_WRAP_0_CC_CNTRL register (where COREID is the name of the specific C7120 core) must be enabled before power-up of the C7120 core to override all clock-gating.