米6体育平台手机版

SPRZ530C April 2022 – July 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1

1
1Modules Affected
2Nomenclature, Package Symbolization, and Revision Identification
3Silicon Revision 1.0 Usage Notes and Advisories
1. 3.1 Silicon Revision 1.0 Usage Notes
  1. i2134
2. 3.2 Silicon Revision 1.0 Advisories
  1. i2049
  2. i2062
  3. i2063
  4. i2064
  5. i2065
  6. i2079
  7. i2091
  8. i2097
  9. i2103
  10. i2120
  11. i2134
  12. i2137
  13. i2146
  14. i2157
  15. i2159
  16. i2160
  17. i2161
  18. i2163
  19. i2166
  20. i2177
  21. i2189
  22. i2190
  23. i2196
  24. i2197
  25. i2205
  26. i2215
  27. i2216
  28. i2219
  29. i2232
  30. i2234
  31. i2235
  32. i2237
  33. i2242
  34. i2243
  35. i2244
  36. i2249
  37. i2253
  38. i2271
  39. i2272
  40. i2278
  41. i2279
  42. i2283
  43. i2307
  44. i2308
  45. i2310
  46. i2311
  47. i2312
  48. i2313
  49. i2316
  50. i2320
  51. i2326
  52. i2329
  53. i2351
  54. i2362
  55. i2366
  56. i2371
  57. i2372
  58. i2378
  59. i2381
  60. i2383
  61. i2399
  62. i2401
  63. i2409
  64. i2414
  65. i2419
  66. i2422
  67. i2435
  68. i2437
Trademarks
Revision History

i2316

DDR: MCU_OSPI0_* pins are limited to 1.8V operation when DDR1 is used

Details

The MCU_OSPI0_* pins are limited to 1.8V operation when DDR1 is used, due to an issue with crosstalk in the package. The MCU_OSPI0_* pins are powered by the VDDSHV1_MCU rail, which also powers the MCU_OSPI1_* pins.

Workaround

There are two options to Workaround this issue if DDR1 is used:

- Power the VDDSHV1_MCU rail at 1.8V. All of the MCU_OSPI0/1_* pins can be operated as normal.

- Power the VDDSHV1_MCU rail at 3.3V. The MCU_OSPI1_* pins can be operated as normal, but the MCU_OSPI0_* pins should be held static with no activity/toggling.