Details:

The shadow copies of the following two MSMC MMRs have the wrong reset value. The main copy that SW can read have the correct reset value, but MSMC functionality uses the value in the shadow copies. The incorrect reset values results in reduced DDR system performance. More specifically MSMC L3 data cache and snoop filter to be under-utilized for DDR accesses (utilization drops to 25% of expectations). The under-utilization extends to the L2 cache of the A72 [include in J7AEP-only: "and C7x"].

RT_WAY_SELECT [Address = 0x6E00_8000]

NRT_WAY_SELECT [Address = 0x6E00_8008]

Workaround(s):

SW needs to write the value (0x0000_0303) to both MSMC MMRs after reset. This is needed even if the MMRs appear to already have the correct value. Writing to the MMRs ensure that their shadow copies have the correct post-reset value.