SPRZ530C April 2022 – July 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
PCIe: SERDES0_REFCLK_P/N SerDes Reference Clock Output does not comply to Vcross, Rise-Fall Matching, and Edge Rate limits
The SERDES0_REFCLK_P/N PCIe Reference Clock Output of the SerDes does not comply with the PCI-SIG specifications for VCROSS and Edge Rate limits. Therefore, some external PCIe components may have an issue receiving and using the Reference Clock. However, the SerDes in this Device family does not have an issue accepting this non-compliant Reference Clock. This means that a link that connects the SerDes in one Device to the SerDes in a second Device will not have an issue when one Device generates the Reference Clock and the other Device receives the Reference Clock.
The PCIE_REFCLK1_P/N should instead be used to output the PCIe Refclk.