| ADC |
ADC: ADC-C Does Not Meet 16-bit Mode
Specifications |
Yes |
No |
| ADC |
ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt
Mode) is not Set |
Yes |
Yes |
| DCAN |
During DCAN FIFO Mode, Received Messages May be Placed Out of
Order in the FIFO Buffer |
Yes |
Yes |
| MCAN |
Message Order Inversion When Transmitting From Dedicated Tx
Buffers Configured With Same Message ID |
Yes |
Yes |
| ePWM |
ePWM: An ePWM Glitch can Occur if a Trip Remains Active at the
End of the Blanking Window |
Yes |
Yes |
| ePWM |
ePWM: Trip Events Will Not be Filtered by the Blanking Window
for the First 3 Cycles After the Start of a Blanking
Window |
Yes |
Yes |
| Flash |
Flash: Single-Bit ECC Error Interrupt is Not
Generated |
Yes |
Yes |
| FPU |
FPU: FPU-to-CPU Register Move Operation Preceded by Any FPU 2p
Operation |
Yes |
Yes |
| GPIO |
GPIO: Open-Drain Configuration may Drive a Short High
Pulse |
Yes |
Yes |
| I2C |
I2C: Target Transmitter Mode, Standard Mode SDA Timings
Limitation |
Yes |
Yes |
| MCD |
MCD: Missing Clock Detect Should be Disabled When the PLL is
Enabled (PLLCLKEN = 1) |
Yes |
Yes |
| Memory |
Memory: Prefetching Beyond Valid Memory |
Yes |
Yes |
| MPOST |
MPOST: Execution of Memory Power-On Self-Test will not Execute
on Some Early Material |
Yes |
Yes |
| SDFM |
SDFM: Dynamically Changing Threshold Settings (LLT, HLT),
Filter Type, or COSR Settings Will Trigger Spurious Comparator
Events |
Yes |
Yes |
| SDFM |
SDFM: Dynamically Changing Data Filter Settings (Such as Filter
Type or DOSR) Will Trigger Spurious Data Acknowledge
Events |
Yes |
Yes |
| SDFM |
SDFM: Two Back-to-Back Writes to SDCPARMx Register Bit Fields
CEVT1SEL, CEVT2SEL, and HZEN Within Three SD-Modulator Clock
Cycles can Corrupt SDFM State Machine, Resulting in Spurious
Comparator Events |
Yes |
Yes |
| USB |
USB: USB DMA Event Triggers are not Supported |
Yes |
Yes |