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SPRZ569 November 2024 F29H850TU , F29H859TU-Q1

1
TMS320F2838x MCUs Silicon Errata Silicon Revisions A, 0
1Usage Notes and Advisories Matrices
1. 1.1 Usage Notes Matrix
2. 1.2 Advisories Matrix
2Nomenclature, Package Symbolization, and Revision Identification
3Silicon Revision 0 Usage Notes and Advisories
1. 3.1 Silicon Revision 0 Usage Notes
2. 3.2 Silicon Revision 0 Advisories
  1. Advisory
  2. Advisory
  3. 3.2.1 Advisory
  4. Advisory
  5. 3.2.2 Advisory
  6. Advisory
  7. Advisory
  8. Advisory
  9. Advisory
  10. Advisory
  11. 3.2.3 Advisory
  12. 3.2.4 Advisory
  13. 3.2.5 Advisory
  14. 3.2.6 Advisory
4Documentation Support
5Trademarks
6Revision History

3.2.2 Advisory

Flash: Stand-alone CPU1/CPU3 Reset With Flash Prefetch Enabled May Cause NMI to CPU1/CPU3

Revisions Affected

Details

If Flash prefetch is enabled, a stand-alone reset issued to CPU1 or CPU3 (for example, debug reset from CCS) may cause an NMI to the CPU because of an uncorrectable ECC error. Below are the sources for a stand-alone CPU reset.

CPU1:

Debug reset
HSM → CPU1.RSn

CPU3:

Debug reset
HSM → CPU3.RSn
CPU3 WD Reset
CPU3 NMIWD Reset
SSU → CPU_RST_CTRL.SW_SYSRSN

Workaround

Disable Flash prefetch (FRIx_INTF_CTRL.PREFETCH_EN = 0) before issuing a stand-alone reset to the CPU.

CPU1 → FRI1_INTF_CTRL.PREFETCH_EN = 0

CPU3 → FRI3_INTF_CTRL.PREFETCH_EN = 0