| ADC | ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt
Mode) is not Set | Yes |
| DCAN | During DCAN FIFO Mode, Received Messages May be Placed Out of
Order in the FIFO Buffer | Yes |
| MCAN | Message Order Inversion When Transmitting From Dedicated Tx
Buffers Configured With Same Message ID | Yes |
| ePWM | ePWM: An ePWM Glitch can Occur if a Trip Remains Active at the
End of the Blanking Window | Yes |
| Flash |
Flash: Stand-alone CPU1/CPU3 Reset With Flash Prefetch Enabled
May Cause NMI to CPU1/CPU3 |
Yes |
| GPIO | GPIO: Open-Drain Configuration may Drive a Short High
Pulse | Yes |
| MCD | MCD: Missing Clock Detect Should be Disabled When the PLL is
Enabled (PLLCLKEN = 1) | Yes |
| SDFM | SDFM: Dynamically Changing Threshold Settings (LLT, HLT),
Filter Type, or COSR Settings Will Trigger Spurious Comparator
Events | Yes |
| SDFM | SDFM: Dynamically Changing Data Filter Settings (Such as Filter
Type or DOSR) Will Trigger Spurious Data Acknowledge
Events | Yes |
| SDFM | SDFM: Two Back-to-Back Writes to SDCPARMx Register Bit Fields
CEVT1SEL, CEVT2SEL, and HZEN Within Three SD-Modulator Clock
Cycles can Corrupt SDFM State Machine, Resulting in Spurious
Comparator Events | Yes |
| C29 CPU Subsystem |
C29 CPU Subsystem: DTHE Interrupts and DMA Events Not Triggered
in C29 CPU Subsystem for HS-FS Devices |
Yes |
| System |
System: Device Reset Remains Asserted When VDD Voltage Ramps
Before VDDIO |
Yes |
| System |
System: Pending Misaligned Reads in the Pipeline After CPU Goes
to Fault State Preventing NMI Vector Fetch |
Yes |
| UART |
UART: UART FIFO Gets Cleared on Continuous Debugger
Reads |
Yes |