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SPRZ569 November 2024 F29H850TU , F29H859TU-Q1

1
TMS320F2838x MCUs Silicon Errata Silicon Revisions A, 0
1Usage Notes and Advisories Matrices
1. 1.1 Usage Notes Matrix
2. 1.2 Advisories Matrix
2Nomenclature, Package Symbolization, and Revision Identification
3Silicon Revision 0 Usage Notes and Advisories
1. 3.1 Silicon Revision 0 Usage Notes
2. 3.2 Silicon Revision 0 Advisories
  1. Advisory
  2. Advisory
  3. 3.2.1 Advisory
  4. Advisory
  5. 3.2.2 Advisory
  6. Advisory
  7. Advisory
  8. Advisory
  9. Advisory
  10. Advisory
  11. 3.2.3 Advisory
  12. 3.2.4 Advisory
  13. 3.2.5 Advisory
  14. 3.2.6 Advisory
4Documentation Support
5Trademarks
6Revision History

Advisory

SDFM: Two Back-to-Back Writes to SDCPARMx Register Bit Fields CEVT1SEL, CEVT2SEL, and HZEN Within Three SD-Modulator Clock Cycles can Corrupt SDFM State Machine, Resulting in Spurious Comparator Events

Revisions Affected

Details

Back-to-back writes to SDCPARMx register bit fields CEVT1SEL, CEVT2SEL, and HZEN within three SD-modulator clock cycles can potentially corrupt the SDFM state machine, resulting in spurious comparator events, which can potentially trigger CPU interrupts, ePWM XBAR events, and GPIO output X-BAR events if configured appropriately.

Workaround

Avoid back-to-back writes within three SD-modulator clock cycles or have the SDCPARMx register bit fields configured in one register write.