SPRZ570A November   2023  – May 2024 AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3. 1Usage Notes and Advisories Matrices
  4. 2Silicon Revision 1.0 Usage Notes and Advisories
    1. 2.1 Silicon Revision 1.0 Usage Notes
      1.      i2324
    2. 2.2 Silicon Revision 1.0 Advisories
      1.      i2189
      2.      i2310
      3.      i2374
      4.      i2311
      5.      i2345
      6.      i2351
      7.      i2352
      8.      i2353
      9.      i2354
      10.      i2356
      11.      i2357
      12.      i2358
      13.      i2359
      14.      i2383
      15.      i2392
      16.      i2393
      17.      i2394
      18.      i2401
      19.      i2403
      20.      i2404
      21.      i2405
      22.      i2426
      23.      i2427
      24.      i2428
      25.      i2433
      26.      i2438
      27.      i2439
  5. 3Trademarks
  6. 4Revision History

Usage Notes and Advisories Matrices

Table 1-1 lists all usage notes and the applicable silicon revision(s). Table 1-2 lists all advisories, modules affected, and the applicable silicon revision(s).

Table 1-1 Usage Notes Matrix
Module DESCRIPTION SILICON REVISIONS AFFECTED
AM263Px
1.0
CLOCKS i2324 — No synchronizer present between GCM and GCD status signals YES
Table 1-2 Advisories Matrix
MODULE DESCRIPTION SILICON REVISIONS AFFECTED
AM263Px
1.0
CONTROLSS i2352 — CONTROLSS-SDFM: Dynamically Changing Threshold Settings (LLT, HLT), Filter Type, or COSR Settings Will Trigger Spurious Comparator Events YES
CONTROLSS i2353 — CONTROLSS-SDFM: Dynamically Changing Data Filter Settings (Such as Filter Type or DOSR) Will Trigger Spurious Data Acknowledge Events YES
CONTROLSS i2354 — CONTROLSS-SDFM: Two Back-to-Back Writes to SDCPARMx Register Bit Fields CEVT1SEL, CEVT2SEL, and HZEN Within Three SD-Modulator Clock Cycles can Corrupt SDFM State Machine, Resulting in Spurious Comparator Events YES
CONTROLSS i2356 — CONTROLSS-ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt Mode) is not Set YES
CONTROLSS i2357 — CONTROLSS-ePWM: An ePWM Glitch can Occur if a Trip Remains Active at the End of the Blanking Window YES
CONTROLSS i2358 — CONTROLSS-ePWM: Trip Events Will Not be Filtered by the Blanking Window for the First 3 Cycles After the Start of a Blanking YES
CONTROLSS i2359 — CONTROLSS-CMPSS:Prescaler counter behavior different from spec when DACSOURCE is made 0 or reconfigured as 1 YES
CONTROLSS i2405 — CONTROLSS: Race condition OUTPUT_XBAR and PWM_XBAR resulting in event miss YES
CPSW i2345 — CPSW: Ethernet Packet corruption occurs if CPDMA fetches a packet which spans across memory banks YES
CPSW i2401 — CPSW: Host Timestamps Cause CPSW Port to Lock YES
CPSW i2438 — CPSW: Host to Ethernet Checksum Generation with VLAN ADD/Remove YES
CPSW i2439 — CPSW: Host to Ethernet Timestamp Accuracy Issue YES
UART i2310 — USART: Erroneous triggering of timeout interrupt YES
UART i2311 USART Spurious DMA Interrupts — USART: Spurious DMA Interrupts YES
M4 ROM i2403 — M4 ROM: SBL redundant boot image feature not supported on HSSE devices YES
MBOX i2404 — MBOX: Race condition in mailbox registers resulting in events miss YES
ROM i2426 — ROM does not support OSPI 8D boot mode for the flashes supporting extended opcode YES
RAM SEC i2427 — RAM SEC can cause Spurious RAM writes resulting in L2 & MBOX memory corruption YES
DTHE i2428 — AES in DTHE generates extra dma request for data_in at the end of GCM encrypt YES
SOC CONTROL i2394 — Race condition in interrupt and error aggregator capture registers resulting in events miss YES
SOC CONTROL i2392 — Race condition in mem-init capture registers resulting in events miss YES
BUS SAFETY i2393 — Granular error status not logged in BUS_SAFETY_ERR registers for the detected faults YES
OSPI i2383 — OSPI: 2-byte address is not supported in PHY DDR mode YES
OSPI i2351 — OSPI: Direct Access Controller (DAC) does not support Continuous Read mode with NAND Flash YES
OSPI i2189 — OSPI: Controller PHY Tuning Algorithm YES
PBIST i2374 — PBIST: PBIST fails if clock frequency of R5SS_CORE_CLK is not same as R5FSS_CLK_SELECTED frequency YES
ICSS i2433 — ICSS: Reading the 64-bit IEP timer does not have a lock MSW logic when LSW is read YES