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SPRZ572A April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1

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TMS320F28003x Real-Time MCUs Silicon ErrataSilicon Revision 0
1Usage Notes and Advisories Matrices
1. 1.1 Usage Notes Matrix
2. 1.2 Advisories Matrix
2Nomenclature, Package Symbolization, and Revision Identification
3Silicon Revision A Usage Notes and Advisories
1. 3.1 Silicon Revision A Usage Notes
2. 3.2 Silicon Revision A Advisories
  1. Advisory
  2. Advisory
  3. Advisory
  4. Advisory
  5. Advisory
  6. 3.2.1 Advisory
  7. Advisory
  8. 3.2.2 Advisory
  9. Advisory
  10. 3.2.3 Advisory
  11. Advisory
  12. Advisory
  13. 3.2.4 Advisory
  14. Advisory
  15. Advisory
  16. Advisory
  17. Advisory
  18. Advisory
4Silicon Revision 0 Usage Notes and Advisories
1. 4.1 Silicon Revision 0 Usage Notes
2. 4.2 Silicon Revision 0 Advisories
  1. Advisory
  2. Advisory
  3. Advisory
  4. Advisory
  5. 4.2.1 Advisory
5Documentation Support
6Trademarks
7Revision History

Advisory

BOR: VDDIO Between 2.45 V and 3.0 V can Result in Multiple XRSn Pulses

Revisions Affected

0, A

Details

The BOR can generate repeating XRSn assertions and deassertions when the VDDIO supply voltage is between 2.45 V and 3.0 V. It is recommended that the XRSn pin not be used directly as a reset to any other devices in the system.

The F28P55x BOR is effective for internally holding the device in a known reset state, even when these XRSn pulses are occurring. The device will not branch to application code or bootloaders, and all other pins will be held in their reset state until the VDDIO supply rises above 3.0 V.

Workarounds

Ignore the extra XRSn transitions during power up, power down, and BOR events. The extra XRSn pulses will have no effect on the F28P55x device operation itself.
If XRSn pulses would cause undesired system behavior with other system components, then do not use XRSn to drive other devices. An external voltage supervisor can be used for these applications.
For applications that need to avoid these pulses during normal power up and power down:
1. Power up: Follow the SR_SUPPLY requirement in the Recommended Operating Conditions table of the TMS320F28P55x Real-Time Microcontrollers data sheet; no extra XRSn low pulses will occur.
2. Power Down: To avoid any deassertion of XRSn during power down, design the power supply so that VDDIO passes through the range from 3.0 V to 2.45 V within 25 µs. If some voltage rise on XRSn is acceptable, then the time constant of the RC circuit implemented on XRSn can be calculated to ensure the voltage does not rise above a system-specified threshold.