SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The TDC high-speed counter clock source is configurable by DDI_0_OSC: CTL0.ACLK_TDC_SRC_SEL, as listed in Table 20-22.
| ACLK_TDC_SRC_SEL | Oscillator | Frequency (MHz) |
|---|---|---|
| 0x0 | RCOSC_HF | 48 |
| 0x1 | RCOSC_HF | 24 |
| 0x2 | XOSC_HF | 24 |
| 0x3 | Not Used | Not applicable |
Configuration of DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL is done through the DDI Control-Configuration interface. See Section 20.4.1.1 for details.
The user must activate the selected counter clock source before TDC measurements can start:
The user must deactivate the counter clock source when the TDC measurements are complete. Failure to do so will prevent the system from entering standby mode because the Oscillator Control module requests resources from the supply system. To remove the clock source request, clear AUX_SYSIF:TDCCLKCTL.REQ.