SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
25.4.4 I2S
I2S is a dual-phase format with a 50% WCLK duty cycle and the start of an MSB of each sample word aligned with each edge of WCLK + one BCLK period. For any given frame, the left channel is transferred first when WCLK is low, and the right channel is transferred next when WCLK is high. Figure 25-2 shows the I2S serial format.
Data is sampled on the rising edge of BCLK and updated on the falling edge of BCLK.
The I2S format is unique in the sense that the CC13x2x7 and CC26x2x7 device platform can automatically detect the number of BCLK periods per WCLK period. Therefore, I2S supports any BCLK rate from an external audio clock source and also variable sample word length:
- If the configured sample word length is higher than the number of bits per WCLK period, the sample words are truncated.
- If the configured sample word length is lower than the number of bits per WCLK period, the sample words are zero-padded.
Figure 25-2 I2S Serial Format