米6体育平台手机版

SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7

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        382
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                645
        
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                668
        
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690
1. 691
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695
1. 696
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  1. 700
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  7. 710
5. 711
6. 712
7. 713
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715
1. 716
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4. 719
  1. 720
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6. 736
7. 737
  1. 738
739
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    1. 750
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4. 758
5. 759
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761
1. 762
2. 763
3. 764
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    2. 780
5. 781
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6. 789
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7. 794
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9. 798
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800
1. 801
  1. 802
2. 803
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    1. 807
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3. 814
  1. 815
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    4. 820
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    8. 832
  3. 833
    1. 834
      1. 835
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      7. 841
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      14. 848
    2. 849
      1. 850
      2. 851
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      14. 863
      15. 864
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      19. 868
      20. 869
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      1.        898
        
                899
        
                900
      2. 901
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    2. 905
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  5. 910
    1. 911
    2. 912
    3. 913
    4. 914
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6. 917
  1. 918
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      1. 920
    2. 921
    3. 922
    4. 923
  2. 924
7. 925
  1. 926
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8. 928
  1. 929
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  8. 936
    1. 937
    2. 938
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  9. 941
    1. 942
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    3. 944
  10. 945
    1. 946
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    3. 948
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    5. 950
  11. 951
    1. 952
    2. 953
    3. 954
    4. 955
    5. 956
  12. 957
  13. 958
  14. 959
  15. 960
  16. 961
  17. 962
9. 963
  1. 964
10. 965
  1. 966
  2. 967
    1. 968
      1. 969
    2. 970
    3. 971
  3. 972
  4. 973
    1. 974
    2. 975
  5. 976
    1. 977
    2. 978
      1. 979
    3. 980
      1. 981
      2. 982
    4. 983
      1. 984
      2. 985
    5. 986
      1. 987
      2. 988
      3. 989
  6. 990
    1. 991
    2. 992
11. 993
  1. 994
  2. 995
  3. 996
997

3.9.5 CPU_TPIU Registers

#CPU_TPIU_CPU_TPIU_MAP1_TABLE_1 lists the memory-mapped registers for the CPU_TPIU registers. All register offset addresses not listed in #CPU_TPIU_CPU_TPIU_MAP1_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 3-185 CPU_TPIU Registers

Offset	Acronym	Register Name	Section
0h	SSPSR	Supported Sync Port Sizes	#CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_SSPSR
4h	CSPSR	Current Sync Port Size	#CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_CSPSR
10h	ACPR	Async Clock Prescaler	#CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_ACPR
F0h	SPPR	Selected Pin Protocol	#CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_SPPR
300h	FFSR	Formatter and Flush Status	#CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_FFSR
304h	FFCR	Formatter and Flush Control	#CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_FFCR
308h	FSCR	Formatter Synchronization Counter	#CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_FSCR
FA0h	CLAIMMASK	Claim Tag Mask	#CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_CLAIMMASK
FA0h	CLAIMSET	Claim Tag Set	#CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_CLAIMSET
FA4h	CLAIMTAG	Current Claim Tag	#CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_CLAIMTAG
FA4h	CLAIMCLR	Claim Tag Clear	#CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_CLAIMCLR
FC8h	DEVID	Device ID	#CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_DEVID

Complex bit access types are encoded to fit into small table cells. #CPU_TPIU_CPU_TPIU_MAP1_LEGEND shows the codes that are used for access types in this section.

Table 3-186 CPU_TPIU Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

3.9.5.1 SSPSR Register (Offset = 0h) [Reset = 0000000Bh]

SSPSR is shown in #CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_SSPSR_FIGURE and described in #CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_SSPSR_TABLE.

Return to the Summary Table.

Supported Sync Port Sizes
This register represents a single port size that is supported on the device, that is, 4, 2 or 1. This is to ensure that tools do not attempt to select a port width that an attached TPA cannot capture.

Figure 3-149 SSPSR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				FOUR	THREE	TWO	ONE
R-0h				R-1h	R-0h	R-1h	R-1h

Table 3-187 SSPSR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3	FOUR	R	1h	4-bit port size support 0x0: Not supported 0x1: Supported
2	THREE	R	0h	3-bit port size support 0x0: Not supported 0x1: Supported
1	TWO	R	1h	2-bit port size support 0x0: Not supported 0x1: Supported
0	ONE	R	1h	1-bit port size support 0x0: Not supported 0x1: Supported

3.9.5.2 CSPSR Register (Offset = 4h) [Reset = 00000001h]

CSPSR is shown in #CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_CSPSR_FIGURE and described in #CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_CSPSR_TABLE.

Return to the Summary Table.

Current Sync Port Size
This register has the same format as SSPSR but only one bit can be set, and all others must be zero. Writing values with more than one bit set, or setting a bit that is not indicated as supported can cause Unpredictable behavior. On reset this defaults to the smallest possible port size, 1 bit.

Figure 3-150 CSPSR Register

31	30	29	28	27	26	25	24
RESERVED
R/W-0h

23	22	21	20	19	18	17	16
RESERVED
R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R/W-0h

7	6	5	4	3	2	1	0
RESERVED				FOUR	THREE	TWO	ONE
R/W-0h				R/W-0h	R/W-0h	R/W-0h	R/W-1h

Table 3-188 CSPSR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R/W	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3	FOUR	R/W	0h	4-bit port enable Writing values with more than one bit set in CSPSR, or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior.
2	THREE	R/W	0h	3-bit port enable Writing values with more than one bit set in CSPSR, or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior.
1	TWO	R/W	0h	2-bit port enable Writing values with more than one bit set in CSPSR, or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior.
0	ONE	R/W	1h	1-bit port enable Writing values with more than one bit set in CSPSR, or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior.

3.9.5.3 ACPR Register (Offset = 10h) [Reset = 00000000h]

ACPR is shown in #CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_ACPR_FIGURE and described in #CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_ACPR_TABLE.

Return to the Summary Table.

Async Clock Prescaler
This register scales the baud rate of the asynchronous output.

Figure 3-151 ACPR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																			PRESCALER
R/W-0h																			R/W-0h

Table 3-189 ACPR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-13	RESERVED	R/W	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
12-0	PRESCALER	R/W	0h	Divisor for input trace clock is (PRESCALER + 1).

3.9.5.4 SPPR Register (Offset = F0h) [Reset = 00000001h]

SPPR is shown in #CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_SPPR_FIGURE and described in #CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_SPPR_TABLE.

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Selected Pin Protocol
This register selects the protocol to be used for trace output.
Note: If this register is changed while trace data is being output, data corruption occurs.

Figure 3-152 SPPR Register

31	30	29	28	27	26	25	24
RESERVED
R/W-0h

23	22	21	20	19	18	17	16
RESERVED
R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R/W-0h

7	6	5	4	3	2	1	0
RESERVED						PROTOCOL
R/W-0h						R/W-1h

Table 3-190 SPPR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R/W	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0	PROTOCOL	R/W	1h	Trace output protocol 0h = TracePort mode 1h = SerialWire Output (Manchester). This is the reset value. 2h = SerialWire Output (NRZ)

Bit

Field

Type

Reset

Description

31-2

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

1-0

PROTOCOL

R/W

Trace output protocol

0h = TracePort mode

1h = SerialWire Output (Manchester). This is the reset value.

2h = SerialWire Output (NRZ)

3.9.5.5 FFSR Register (Offset = 300h) [Reset = 00000008h]

FFSR is shown in #CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_FFSR_FIGURE and described in #CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_FFSR_TABLE.

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Formatter and Flush Status

Figure 3-153 FFSR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				FTNONSTOP	RESERVED
R-0h				R-1h	R-0h

Table 3-191 FFSR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3	FTNONSTOP	R	1h	0: Formatter can be stopped 1: Formatter cannot be stopped
2-0	RESERVED	R	0h	This field always reads as zero

3.9.5.6 FFCR Register (Offset = 304h) [Reset = 00000102h]

FFCR is shown in #CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_FFCR_FIGURE and described in #CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_FFCR_TABLE.

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Formatter and Flush Control
When one of the two single wire output (SWO) modes is selected, ENFCONT enables the formatter to be bypassed. If the formatter is bypassed, only the ITM/DWT trace source (ATDATA2) passes through. The TPIU accepts and discards data that is presented on the ETM port (ATDATA1). This function is intended to be used when it is necessary to connect a device containing an ETM to a trace capture device that is only able to capture Serial Wire Output (SWO) data. Enabling or disabling the formatter causes momentary data corruption.
Note: If the selected pin protocol register (SPPR.PROTOCOL) is set to 0x00 (TracePort mode), this register always reads 0x102, because the formatter is automatically enabled. If one of the serial wire modes is then selected, the register reverts to its previously programmed value.

Figure 3-154 FFCR Register

31	30	29	28	27	26	25	24
RESERVED
R/W-0h

23	22	21	20	19	18	17	16
RESERVED
R/W-0h

15	14	13	12	11	10	9	8
RESERVED							TRIGIN
R/W-0h							R/W-1h

7	6	5	4	3	2	1	0
RESERVED						ENFCONT	RESERVED
R/W-0h						R/W-1h	R/W-0h

Table 3-192 FFCR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R/W	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
8	TRIGIN	R/W	1h	Indicates that triggers are inserted when a trigger pin is asserted.
7-2	RESERVED	R/W	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1	ENFCONT	R/W	1h	Enable continuous formatting: 0: Continuous formatting disabled 1: Continuous formatting enabled
0	RESERVED	R/W	0h	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

3.9.5.7 FSCR Register (Offset = 308h) [Reset = 00000000h]

FSCR is shown in #CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_FSCR_FIGURE and described in #CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_FSCR_TABLE.

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Formatter Synchronization Counter

Figure 3-155 FSCR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FSCR
R-0h

Table 3-193 FSCR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	FSCR	R	0h	The global synchronization trigger is generated by the Program Counter (PC) Sampler block. This means that there is no synchronization counter in the TPIU.

3.9.5.8 CLAIMMASK Register (Offset = FA0h) [Reset = 0000000Fh]

CLAIMMASK is shown in #CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_CLAIMMASK_FIGURE and described in #CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_CLAIMMASK_TABLE.

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Claim Tag Mask

Figure 3-156 CLAIMMASK Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLAIMMASK
R-Fh

Table 3-194 CLAIMMASK Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	CLAIMMASK	R	Fh	This register forms one half of the Claim Tag value. When reading this register returns the number of bits that can be set (each bit is considered separately): 0: This claim tag bit is not implemented 1: This claim tag bit is not implemented The behavior when writing to this register is described in CLAIMSET.

3.9.5.9 CLAIMSET Register (Offset = FA0h) [Reset = 0000000Fh]

CLAIMSET is shown in #CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_CLAIMSET_FIGURE and described in #CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_CLAIMSET_TABLE.

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Claim Tag Set

Figure 3-157 CLAIMSET Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLAIMSET
W-Fh

Table 3-195 CLAIMSET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	CLAIMSET	W	Fh	This register forms one half of the Claim Tag value. Writing to this location allows individual bits to be set (each bit is considered separately): 0: No effect 1: Set this bit in the claim tag The behavior when reading from this location is described in CLAIMMASK.

3.9.5.10 CLAIMTAG Register (Offset = FA4h) [Reset = 00000000h]

CLAIMTAG is shown in #CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_CLAIMTAG_FIGURE and described in #CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_CLAIMTAG_TABLE.

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Current Claim Tag

Figure 3-158 CLAIMTAG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLAIMTAG
R-0h

Table 3-196 CLAIMTAG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	CLAIMTAG	R	0h	This register forms one half of the Claim Tag value. Reading this register returns the current Claim Tag value. Reading CLAIMMASK determines how many bits from this register must be used. The behavior when writing to this register is described in CLAIMCLR.

3.9.5.11 CLAIMCLR Register (Offset = FA4h) [Reset = 00000000h]

CLAIMCLR is shown in #CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_CLAIMCLR_FIGURE and described in #CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_CLAIMCLR_TABLE.

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Claim Tag Clear

Figure 3-159 CLAIMCLR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLAIMCLR
W-0h

Table 3-197 CLAIMCLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	CLAIMCLR	W	0h	This register forms one half of the Claim Tag value. Writing to this location enables individual bits to be cleared (each bit is considered separately): 0: No effect 1: Clear this bit in the claim tag. The behavior when reading from this location is described in CLAIMTAG.

3.9.5.12 DEVID Register (Offset = FC8h) [Reset = 00000CA0h]

DEVID is shown in #CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_DEVID_FIGURE and described in #CPU_TPIU_CPU_TPIU_MAP1_CPU_TPIU_ALL_DEVID_TABLE.

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Device ID

Figure 3-160 DEVID Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEVID
R-CA0h

Table 3-198 DEVID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	DEVID	R	CA0h	This field returns: 0xCA1 if there is an ETM present. 0xCA0 if there is no ETM present.