米6体育平台手机版

SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7

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        382
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690
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695
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7. 713
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715
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7. 737
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5. 781
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6. 789
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800
1. 801
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    2. 849
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      20. 869
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                900
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    1. 911
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6. 917
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    3. 922
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7. 925
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8. 928
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    1. 937
    2. 938
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    1. 942
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  10. 945
    1. 946
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    3. 948
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    5. 950
  11. 951
    1. 952
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    5. 956
  12. 957
  13. 958
  14. 959
  15. 960
  16. 961
  17. 962
9. 963
  1. 964
10. 965
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  2. 967
    1. 968
      1. 969
    2. 970
    3. 971
  3. 972
  4. 973
    1. 974
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  5. 976
    1. 977
    2. 978
      1. 979
    3. 980
      1. 981
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    4. 983
      1. 984
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    5. 986
      1. 987
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      3. 989
  6. 990
    1. 991
    2. 992
11. 993
  1. 994
  2. 995
  3. 996
997

20.8.12 AUX_SCE Registers

#AUX_SCE_AUX_SCE_MMAP_AUX_SCE_TABLE_1 lists the memory-mapped registers for the AUX_SCE registers. All register offset addresses not listed in #AUX_SCE_AUX_SCE_MMAP_AUX_SCE_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 20-270 AUX_SCE Registers

Offset	Acronym	Register Name	Section
0h	CTL	Internal	#AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_CTL
4h	FETCHSTAT	Internal	#AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_FETCHSTAT
8h	CPUSTAT	Internal	#AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_CPUSTAT
Ch	WUSTAT	Internal	#AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_WUSTAT
10h	REG1_0	Internal	#AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_REG1_0
14h	REG3_2	Internal	#AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_REG3_2
18h	REG5_4	Internal	#AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_REG5_4
1Ch	REG7_6	Internal	#AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_REG7_6
20h	LOOPADDR	Internal	#AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_LOOPADDR
24h	LOOPCNT	Internal	#AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_LOOPCNT

Complex bit access types are encoded to fit into small table cells. #AUX_SCE_AUX_SCE_MMAP_AUX_SCE_LEGEND shows the codes that are used for access types in this section.

Table 20-271 AUX_SCE Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

20.8.12.1 CTL Register (Offset = 0h) [Reset = 00000000h]

CTL is shown in #AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_CTL_FIGURE and described in #AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_CTL_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 20-244 CTL Register

31	30	29	28	27	26	25	24
FORCE_EV_LOW
R/W-0h

23	22	21	20	19	18	17	16
FORCE_EV_HIGH
R/W-0h

15	14	13	12	11	10	9	8
RESET_VECTOR
R/W-0h

7	6	5	4	3	2	1	0
RESERVED	DBG_FREEZE_EN	FORCE_WU_LOW	FORCE_WU_HIGH	RESTART	SINGLE_STEP	SUSPEND	CLK_EN
R-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 20-272 CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	FORCE_EV_LOW	R/W	0h	Internal. Only to be used through TI provided API.
23-16	FORCE_EV_HIGH	R/W	0h	Internal. Only to be used through TI provided API.
15-8	RESET_VECTOR	R/W	0h	Internal. Only to be used through TI provided API.
7	RESERVED	R	0h	Reserved
6	DBG_FREEZE_EN	R/W	0h	Internal. Only to be used through TI provided API.
5	FORCE_WU_LOW	R/W	0h	Internal. Only to be used through TI provided API.
4	FORCE_WU_HIGH	R/W	0h	Internal. Only to be used through TI provided API.
3	RESTART	R/W	0h	Internal. Only to be used through TI provided API.
2	SINGLE_STEP	R/W	0h	Internal. Only to be used through TI provided API.
1	SUSPEND	R/W	0h	Internal. Only to be used through TI provided API.
0	CLK_EN	R/W	0h	Internal. Only to be used through TI provided API.

20.8.12.2 FETCHSTAT Register (Offset = 4h) [Reset = 00000000h]

FETCHSTAT is shown in #AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_FETCHSTAT_FIGURE and described in #AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_FETCHSTAT_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 20-245 FETCHSTAT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OPCODE																PC
R-0h																R-0h

Table 20-273 FETCHSTAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	OPCODE	R	0h	Internal. Only to be used through TI provided API.
15-0	PC	R	0h	Internal. Only to be used through TI provided API.

20.8.12.3 CPUSTAT Register (Offset = 8h) [Reset = 00000000h]

CPUSTAT is shown in #AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_CPUSTAT_FIGURE and described in #AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_CPUSTAT_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 20-246 CPUSTAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED				BUS_ERROR	SLEEP	WEV	HALTED
R-0h				R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED				V_FLAG	C_FLAG	N_FLAG	Z_FLAG
R-0h				R-0h	R-0h	R-0h	R-0h

Table 20-274 CPUSTAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11	BUS_ERROR	R	0h	Internal. Only to be used through TI provided API.
10	SLEEP	R	0h	Internal. Only to be used through TI provided API.
9	WEV	R	0h	Internal. Only to be used through TI provided API.
8	HALTED	R	0h	Internal. Only to be used through TI provided API.
7-4	RESERVED	R	0h	Reserved
3	V_FLAG	R	0h	Internal. Only to be used through TI provided API.
2	C_FLAG	R	0h	Internal. Only to be used through TI provided API.
1	N_FLAG	R	0h	Internal. Only to be used through TI provided API.
0	Z_FLAG	R	0h	Internal. Only to be used through TI provided API.

20.8.12.4 WUSTAT Register (Offset = Ch) [Reset = 00000000h]

WUSTAT is shown in #AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_WUSTAT_FIGURE and described in #AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_WUSTAT_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 20-247 WUSTAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED					EXC_VECTOR
R-0h					R-0h

15	14	13	12	11	10	9	8
RESERVED							WU_SIGNAL
R-0h							R-0h

7	6	5	4	3	2	1	0
EV_SIGNALS
R-0h

Table 20-275 WUSTAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-19	RESERVED	R	0h	Reserved
18-16	EXC_VECTOR	R	0h	Internal. Only to be used through TI provided API.
15-9	RESERVED	R	0h	Reserved
8	WU_SIGNAL	R	0h	Internal. Only to be used through TI provided API.
7-0	EV_SIGNALS	R	0h	Internal. Only to be used through TI provided API.

20.8.12.5 REG1_0 Register (Offset = 10h) [Reset = 00000000h]

REG1_0 is shown in #AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_REG1_0_FIGURE and described in #AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_REG1_0_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 20-248 REG1_0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REG1																REG0
R-0h																R-0h

Table 20-276 REG1_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	REG1	R	0h	Internal. Only to be used through TI provided API.
15-0	REG0	R	0h	Internal. Only to be used through TI provided API.

20.8.12.6 REG3_2 Register (Offset = 14h) [Reset = 00000000h]

REG3_2 is shown in #AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_REG3_2_FIGURE and described in #AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_REG3_2_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 20-249 REG3_2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REG3																REG2
R-0h																R-0h

Table 20-277 REG3_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	REG3	R	0h	Internal. Only to be used through TI provided API.
15-0	REG2	R	0h	Internal. Only to be used through TI provided API.

20.8.12.7 REG5_4 Register (Offset = 18h) [Reset = 00000000h]

REG5_4 is shown in #AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_REG5_4_FIGURE and described in #AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_REG5_4_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 20-250 REG5_4 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REG5																REG4
R-0h																R-0h

Table 20-278 REG5_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	REG5	R	0h	Internal. Only to be used through TI provided API.
15-0	REG4	R	0h	Internal. Only to be used through TI provided API.

20.8.12.8 REG7_6 Register (Offset = 1Ch) [Reset = 00000000h]

REG7_6 is shown in #AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_REG7_6_FIGURE and described in #AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_REG7_6_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 20-251 REG7_6 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REG7																REG6
R-0h																R-0h

Table 20-279 REG7_6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	REG7	R	0h	Internal. Only to be used through TI provided API.
15-0	REG6	R	0h	Internal. Only to be used through TI provided API.

20.8.12.9 LOOPADDR Register (Offset = 20h) [Reset = 00000000h]

LOOPADDR is shown in #AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_LOOPADDR_FIGURE and described in #AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_LOOPADDR_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 20-252 LOOPADDR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
STOP																START
R-0h																R-0h

Table 20-280 LOOPADDR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	STOP	R	0h	Internal. Only to be used through TI provided API.
15-0	START	R	0h	Internal. Only to be used through TI provided API.

20.8.12.10 LOOPCNT Register (Offset = 24h) [Reset = 00000000h]

LOOPCNT is shown in #AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_LOOPCNT_FIGURE and described in #AUX_SCE_AUX_SCE_MMAP_AUX_SCE_AUX_SCE_ALL_LOOPCNT_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 20-253 LOOPCNT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								ITER_LEFT
R-0h								R-0h

Table 20-281 LOOPCNT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	ITER_LEFT	R	0h	Internal. Only to be used through TI provided API.