SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
| Bit | Field | Width | Type | Reset | Description |
|---|---|---|---|---|---|
| 23–8 | Reserved | 16 | R/W | 0 | Reserved |
| 7 | KeepPoweredinTLR | 1 | R/W | 0 | When 1, the JTAG power domain stays on even in the Test Logic Reset (TLR) state. When 0, the JTAG power domain will be powered down in the Test Logic Reset (TLR) state if ICEPick is visible and TMS is 1. |
| 6 | BlockSysReset | 1 | R/W | 0 | When1, the device system reset signal is blocked. |
| 5–1 | Reserved | 5 | R/W | 0 | Reserved |
| 0 | SystemReset | 1 | R/W | 0 | Emulator controlled System Reset This signal provides the scan controller with the ability to assert the system warm reset. When a 1 is written, this behaves as if the external chip warm reset signal had been momentarily asserted. This signal does not reset any emulation logic. This is a self-clearing bit. This is cleared by the assertion of the reset requested. Writing a 0 has no effect. |