This section describes the NVIC and the registers it uses. The NVIC supports:
- 34 interrupt lines
- A programmable priority level of 0 to 7 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority.
- Low-latency exception and interrupt handling
- Level and pulse detection of interrupt signals
- Dynamic reprioritization of interrupts
- Grouping of priority values into group priority and sub-priority fields
- Interrupt tail chaining
- An external nonmaskable interrupt (NMI)
The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead, providing low-latency exception handling.