The following software example in pseudocode describes the actions that are typically executed by the host software to encrypt and authenticate a message (AAD and payload data), stored in external memory, with AES-CCM mode. The encrypted result is placed into a preallocated area in external memory. The result TAG is read using the slave interface.

The following sequence processes a packet of at least 1 byte of AAD data and at least 1 crypto data byte.

// configure the master control module 
write ALGSEL 0x0000_0002 // enable the DMA path to the AES engine 
write IRQCLR 0x0000_0001 // clear any outstanding events
// configure the key store to provide pre-loaded AES key 
write KEYREADAREA 0x0000_0000 // load the key from ram area 0 (NOTE: The key
              // must be pre-loaded to this area)
wait KEYREADAREA[31]==’0’ // wait until the key is loaded to the AES module
check IRQSTAT[29] = ‘0’// check that the key is loaded without errors
// write the initialization vector 
write AESIV_0
...
write AESIV_3
// configure the AES engine 
write AESCTL = 0b0010_0000_0101_1100_
             0000_0000_0100_1100 // program AES-CCM-128 encryption (M=1, L=3)
write AESDATALEN0// write the length of the crypto block (lo)
write AESDATALEN1// write the length of the crypto block (hi)
              // (may be non-block size aligned)
write AESAUTHLEN // write the length of the AAD data block
              // (may be non-block size aligned)
// configure DMAC to fetch the AAD data 
write DMACH0CTL 0x0000_00001 // enable DMA channel 0
write DMACH0EXTADDR <address> // base address of the AAD input data in ext. memory
write DMACH0LEN <length> // AAD data length in bytes, equal to the AAD
             // length len({aad data})
             // (may be non-block size aligned)
// wait for completion of the AAD data transfer 
wait IRQSTAT[1]==’1’// wait for DMA_IN_DONE
check IRQSTAT[31]==‘0’// check for the absence of errors
// configure DMAC
write DMACH0CTL 0x0000_00001 // enable DMA channel 0
write DMACH0EXTADDR <address> // base address of the payload data in ext. memory
write DMACH0LEN <length> // payload data length in bytes, equal to the message
              // length len({crypto_data})
write DMACH1CTL 0x0000_00001 // enable DMA channel 1
write DMACH1EXTADDR <address> // base address of the output data buffer
write DMACH1LEN <length> // output data length in bytes, equal to the result
              // data length len({crypto data})
// wait for completion 
wait IRQSTAT[0]==’1’// wait for operation completed
check IRQSTAT[31]==‘0’// check for the absence of errors
write ALGSEL 0x0000_0000 // disable the master control/DMA clock
// read tag 
wait AESCTL[30]==’1‘ // wait for the SAVED_CONTEXT_RDY bit [30]
read AESTAGOUT 0 -
  AESTAGOUT 3 // this read clears the ‘saved_context_ready’ flag
// end of algorithm