SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
This section describes the operation of the various timer modes. When using Timer A and Timer B in concatenated mode, only the Timer A control and status bits must be used; there is no need to use the Timer B control and status bits. The GPTM is placed into individual or split mode by writing a value of 0x4 to the GPTM Configuration register (GPT:CFG). In the following sections, the variable n is used in bit field and register names to imply either a Timer A function or a Timer B function. Throughout this section, the time-out event in down-count mode is 0x0; in up-count mode the time-out event is the value in the GPTM Interval Load register (GPT:TnILR) and the optional GPTM Timer n Prescale register (GPT:TnPR).