SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
20.5.5.2.3 Sample Clock
The DAC sample clock charges and maintains the DAC voltage stored in the S-H capacitor. The DAC sample clock waveform consists of a setup phase followed by a hold phase. The sample clock frequency is generally higher in the setup phase compared to the hold phase.
In the setup phase the sample-and-hold capacitor charges to the target voltage, while the hold phase maintains the S-H voltage. Power can be saved by reducing the sample clock frequency in the hold phase. Figure 20-33 shows the concept.
Figure 20-33 DAC Sample Clock Phases
The sample clock period is configured by AUX_ANAIF:DACSMPLCFG0 and AUX_ANAIF:DACSMPLCFG1 registers and enabled by the AUX_ANAIF:DACSMPLCTL register. The sample clock period scales with the peripheral clock frequency set by AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE. Figure 20-34 shows how the sample clock period derives from the peripheral clock.
Figure 20-34 Sample Clock Period Configuration
AUX_ANAIF:DACSMPLCFG0 controls the clock division from the peripheral clock to the sample base clock. The AUX_ANAIF:DACSMPLCFG0 register is set to 2 in Figure 20-34.
AUX_ANAIF:DACSMPLCFG.H_PER and AUX_ANAIF:DACSMPLCFG.L_PER specify the duration of the high and low phase, respectively, of a single sample clock period in terms of the base clock period. They are both set to 2 periods in Figure 20-34.
A state machine can control the transition from setup phase to hold phase, or the user can control this manually.