SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The AES module has two interrupt outputs; both are driven from the master control module and are controlled by the respective registers (see Section 13.5.4.3).
To enable interrupts for the AES engine, the IRQTYPE.EN bit must be set and the interrupt source must be configured in the IRQEN register.
The IRQCLR register is available to clear an interrupt output and error-status bit. The IRQSET register provides the software a way to test the interrupt connections and must be used for debugging only.
The IRQSTAT register provides the status of the two interrupts and error status messages. The error status bits are asserted when they are detected, and typically the value of DMA_BUS_ERR and KEY_ST_WR_ERR signals are valid after the RESULT_AVAIL bit is asserted. The KEY_ST_RD_ERR bit is valid after triggering the key-store module to read a key from memory and providing it to the AES engine.
An interrupt RESULT_AVAIL is activated when an operation that uses DMA is finished. The signal asserts when both the DMA and internal module are in the IDLE state.
Another interrupt DMA_IN_DONE is activated when only the input DMA is finished and is intended for debugging.
Interrupt outputs are not triggered for operations where the DMA is not used.