SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
Sending commands to the radio is done through the CMDR register, while the CMDSTA read-only register provides status back from the radio. The CMDR register can only be written while it reads 0; otherwise, writes are ignored. When the CMDR register is 0 and a nonzero value is written to it, the radio CPU is notified and the CMDSTA register becomes 0. After this action, the value written is readable from the CMDR register until the radio CPU has processed the command, at which point it goes back to 0.
When the command is processed by the radio CPU, the CMDSTA register contains a nonzero status, which is provided at the same instant when the CMDR register goes back to 0. At this instant, an RFCMDACK interrupt occurs. This interrupt is also mapped to the RFACKIFG register, which should be cleared when the interrupt is processed.
See Section 26.3.2 for the format of the command and status registers.