SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
Each peripheral that supports μDMA has a single request or burst request signal that is asserted when the peripheral is ready to transfer data (see Table 15-2). The request signal can be disabled or enabled using the UDMA:SETREQMASK and UDMA:CLEARREQMASK registers, respectively. The μDMA request signal is disabled, or masked, when the channel request mask bit is set. When the request is not masked, the μDMA channel is configured correctly and enabled, the peripheral asserts the request signal, and the μDMA controller begins the transfer.
The peripheral must disable all interrupts to the event fabric when using μDMA to transfer data to and from a peripheral.
When a μDMA transfer is complete, the μDMA controller generates an interrupt; for more information, see Section 15.3.10.
For more information on how a specific peripheral interacts with the μDMA controller, refer to the DMA Operation section in the chapter that discusses that peripheral.