SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output clock. The bit rates are supported to 2 MHz and higher, with maximum bit rate is determined by peripheral devices.
The serial bit rate is derived by dividing down the input clock (SysClk). First, the clock is divided by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale register (SSI:CPSR) (see Section 23.7.1). The clock is further divided by a value from 1 to 256, which is 1 + SCR, where SCR is the value programmed in the SSI Control 0 register (SSI:CR0) (see Section 23.7.1).
Equation 8 defines the frequency of the output clock SSIn_CLK.
For slave mode, the core clock (PERDMACLK) must be at least 12 times faster than SSIn_CLK.
For master mode, the core clock (PERDMACLK) must be at least two times faster than SSIn_CLK.