SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The system-level interrupt RF_HW can be produced from a number of low-level interrupts produced by RF core hardware. Interrupt generation at system level may be switched on and off for each source by using the RFHWEN register.
In the case of an event that triggers a low-level interrupt, the corresponding bit in the RFHWIFG register is set to 1. Whenever a bit in RFHWIFG and the corresponding bit in RFHWIEN are both 1, the RF_HW interrupt is raised. This means that the ISR should clear the bits in RFHWIFG that correspond to low-level interrupts that have been processed.
The register description for RFHWIFG in Section 26.11.2 provides a list of the available interrupts. In general, TI does not recommend servicing these interrupts in the System CPU, but the available radio timer channel interrupts may be served this way.
Clearing bits in RFHWIFG is done by writing 0 to those bits, while any bits written to 1 remain unchanged.
When clearing bits in RFHWIFG, interrupts may be lost if a read-modify-write operation is done. Therefore, the same rule applies for the RFHWIFG register as for RFCPEIFG (see Section 26.2.3.1).