The following software example in pseudocode describes the actions that are typically executed by the host software to encrypt and authenticate a message using AES-GCM mode. The message (AAD and payload data) is fetched from external memory and the encrypted result is placed in a preallocated area in the external memory.

The result TAG is read through the slave interface. The following sequence processes a packet of at least 1 byte of AAD data and at least 1 crypto data byte.

// configure the master control module 
write CTRL_ALG_SEL 0x0000_0002 // enable the DMA path to the AES engine 
write CTRL_INT_CLR 0x0000_0001 // clear any outstanding events 
// configure the key store to provide a pre-loaded AES key 
write KEY_STORE_READ_AREA 0x0000_0000 // load the key from ram area 0 (NOTE: The key 
// must be pre-loaded to this area) 
wait KEY_STORE_READ_AREA[31]==’0’ // wait until the key is loaded to the AES module 
check CTRL_INT_STAT[29] = ‘0’ // check that the key is loaded without errors
// write the initialization vector 
write AES_IV_0 
... 
write AES_IV_3 
// configure the AES engine 
write AES_CTRL = 0b0010_0000_0000_0011_ 
0000_0000_0100_1100 // program AES-GCM-128 encryption (autonomous) 
write AES_C_LENGTH_0 // write the length of the crypto block (lo) 
write AES_C_LENGTH_1 // write the length of the crypto block (hi)
                     // (may be non-block size aligned)
write AES_AUTH_LENGTH // write the length of the AAD data block
// (may be non-block size aligned) 
// configure DMAC to fetch the AAD data
write DMAC_CH0_CTRL 0x0000_00001 // enable DMA channel 0
write DMAC_CH0_EXTADDR <address> // base address of the AAD data in ext. memory
write DMAC_CH0_DMALENGTH <length> // AAD data length in bytes, equal to the aad
// length len({aad data}) 
// (may be non-block size aligned) 
// wait for completion of the AAD data transfer 
wait CTRL_INT_STAT[1]==’1’ // wait for DMA_IN_DONE 
check CTRL_INT_STAT[31]==‘0’ // check for the absence of errors 
// configure DMAC to process the payload data 
write DMAC_CH0_CTRL 0x0000_00001 // enable DMA channel 0
write DMAC_CH0_EXTADDR <address> // base address of the payload data in ext. memory
write DMAC_CH0_DMALENGTH <length> // payload data length in bytes, equal to the payload
// length len({crypto_data}) 
// (may be non-block size aligned) 
write DMAC_CH1_CTRL 0x0000_00001 // enable DMA channel 1
write DMAC_CH1_EXTADDR <address> // base address of the output data buffer
write DMAC_CH1_DMALENGTH <length> // output data length in bytes, equal to the result
// data length len({crypto data}) 
// (may be non-block size aligned) 

// wait for completion 
wait CTRL_INT_STAT[0]==’1’ // wait for operation completed 
check CTRL_INT_STAT[31]==‘0’ // check for the absence of errors 
write CTRL_ALG_SEL 0x0000_0000 // disable the master control/DMA clock 
// read tag 
wait AES_CTRL[30]==’1’ // wait for the context ready bit [30] 
read AES_TAG_OUT_0 
... 
read AES_TAG_OUT_3 // this read clears the ‘saved_context_ready’ flag 
// end of algorithm