SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The audio clocks signals, MCLK, BCLK, and WCLK, can be generated either internally by the PRCM module or by an external clock source.
The internally generated audio clock signals might not be suitable for all applications for the reasons that follow:
When using the internally generated audio clock, the 48 MHz high-frequency system clock, SCLK_HF, must always be derived from XOSC_HF. This derivation is done to reduce jitter and to avoid side-effects of switching the SCLK_HF source from RCOSC_HF to XOSC_HF (missing clock cycles and frequency shift).