SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
| Address Offset | Reset | 0x0000 0000 | |
| Physical Address | Instance | ||
| Description | |||
| The Priority Mask (PRIMASK) register prevents activation of all exceptions with programmable priority. Reset, nonmaskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions must be disabled when they might impact the timing of critical tasks. This register is accessible only in privileged mode. The MSR and MRS instructions are used to access the PRIMASK register, and the CPS instruction may be used to change the value of the PRIMASK register. For more information on these instructions, see Cortex-M3/M4F Instruction Set Technical User's Manual . For more information on exception priority levels, see Section 6.1.2. | |||
| Type | R/W | ||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PRIMASK | ||||||||||||||||||||||||||||||
| Bits | Field Name | Description | Type | Reset | |
|---|---|---|---|---|---|
| 31–1 | RESERVED | Software must not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit must be preserved across a read-modify-write operation. | R/O | 0x0000 000 | |
| 0 | PRIMASK | Priority Mask | R/W | 0 | |
| Value | Description | ||||
| 1 | Prevents the activation of all exceptions with configurable priority | ||||
| 0 | No effect | ||||