SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
Section 3.7.3.1 shows the FP system registers in the Arm® Cortex®-M4F processor, if your implementation includes the FPU.
| Address | Name | Type | Reset | Description |
|---|---|---|---|---|
| 0xE000 EF34 | FPCCR | R/W | 0xC000 0000 | FP Context Control Register |
| 0xE000 EF38 | FPCAR | R/W | – | FP Context Address Register |
| 0xE000 EF3C | FPDSCR | R/W | 0x0000 0000 | FP Default Status Control Register |
| 0xE000 EF40 | MVFR0 | R/O | 0x1011 0021 | Media and VFP Feature Register 0, MVFR0 |
| 0xE000 EF44 | MVFR1 | R/O | 0x1100 0011 | Media and VFP Feature Register 1, MVFR1 |
All Arm® Cortex®-M4F FPU registers are described in the ARMv7-M Architecture Reference Manual.