SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The FPU sets the cumulative exception status flag in the FPSCR register as required for each instruction, in accordance with the FPv4 architecture. The FPU does not support exception traps. The processor also has the following six output pins that each reflect the status of one of the cumulative exception flags:
See the Cortex-M4 Integration and Implementation Manual for a description of these six outputs.
The processor can reduce the exception latency by using lazy stacking. This means that the processor reserves space on the stack for the FP state, but does not save that state information to the stack unless the processor executes an FPU instruction in the current exception handler.
The lazy save of the FP state is interruptible by a higher priority exception. The FP state saving operation starts over after that exception returns.
See the ARMv7-M Architecture Reference Manual for more information.