SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
23.4.4.1 Texas Instruments Synchronous Serial Frame Format
Figure 23-2 shows the TI synchronous serial frame format for a single transmitted frame.
Figure 23-2 TI Synchronous Serial Frame Format (Single Transfer)
SSIn_CLK and SSIn_FSS are forced low and the transmit data line SSIn_TX is put in tristate whenever the SSI is idle. When the bottom entry of the TX FIFO contains data, SSIn_FSS is pulsed high for one SSIn_CLK period. The transmitted value is also transferred from the TX FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIn_CLK, the MSB of the 4- to 16-bit data frame is shifted out on the SSIn_TX pin. Likewise, the MSB of the received data is shifted onto the SSIn_RX pin by the off-chip serial slave device.
Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on each falling edge of SSIn_CLK. The received data is transferred from the serial shifter to the RX FIFO on the first rising edge of SSIn_CLK after the least significant bit (LSB) is latched.
Figure 23-3 shows the TI synchronous serial frame format when back-to-back frames are transmitted.
Figure 23-3 TI Synchronous Serial Frame Format (Continuous Transfer)