The CC13x2x7 and CC26x2x7 device platform includes a direct memory access (DMA) controller, known as μDMA. The μDMA controller provides a way to offload data transfer tasks from the Arm^® Cortex^®-M4F processor, allowing for more efficient use of the processor and the available bus bandwidth. The μDMA controller can perform transfers between memory and peripherals. The controller has dedicated channels for each supported on-chip module, and can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transfer more data. The μDMA controller provides the following features:

• Arm PrimeCell® 32-channel configurable µDMA controller
• Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer modes:
  • Basic for simple transfer scenarios
  • Ping-pong for continuous data flow
  • Scatter-gather for a programmable list of arbitrary transfers initiated from a single request
• Highly flexible and configurable channel operation:
  • Independently configured and operated channels
  • Dedicated channels for supported on-chip modules
  • Primary and secondary channel assignments
  • Flexible channel assignments
  • One channel each for receive and transmit paths for bidirectional modules
  • Dedicated channel for software-initiated transfers
  • Per-channel configurable priority scheme
  • Optional software-initiated requests for any channel
• Two levels of priority
• Data sizes of 8, 16, and 32 bits
• Transfer size is programmable in binary steps from 1 to 1024
• Source and destination address increment size of byte, halfword, word, or no increment
• Maskable peripheral requests
• Interrupt on transfer completion with a separate interrupt per channel