SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
There is no retention logic for cryptography registers. The clocks can be enabled or gated by the following PRCM registers:
The cryptography module is enabled and disabled by the SECDMAHWOPT.CRYPTO_EN bit.
To save power, the application can disable the clock to the AES module when not in use. The AES is clock-gated in sleep mode by setting the SECDMACLKGS register CRYPTO_CLK_EN bit. The AES can also be clock-gated in run mode by setting the SECDMACLKGR register CRYPTO_CLK_EN bit.