SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
As Table 6-1 shows, all exceptions have an associated priority, with a lower priority value indicating a higher priority and configurable priorities for all exceptions except reset, and hard fault. If software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. For information about configuring exception priorities, see the System Handlers Priority register (CPU_SCS:SHPRn) and the Interrupt Priority register (CPU_SCS:NVIC_IPRn) in Section 3.9.4.
Configurable priority values for the CC13x2x7 and CC26x2x7 device platform implementation are in the range from 0 to 7. This means that the Reset and Hard fault exceptions, with fixed negative priority values, always have a higher priority than any other exception.
Assigning a higher priority value to IRQ[0] and a lower-priority value to IRQ[1], for example, means that IRQ[1] has higher priority than IRQ[0]. If IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0].
If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. For example, if IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs. If an exception occurs with the same priority as the exception being handled, the handler is not preempted, irrespective of the exception number. However, the status of the new interrupt changes to pending.