SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The I2C master module generates an interrupt when a transaction completes (either transmit or receive), when arbitration is lost, or when an error occurs during a transaction. To enable the I2C master interrupt, software must set the IM bit in the I2C Master Interrupt Mask register, I2C:MIMR. When an interrupt condition is met, software must check the I2C Master Control and Status register (I2C:MSTAT) ERR and ARBLST bits to verify that an error did not occur during the last transaction, and to ensure that arbitration has not been lost. An error condition is asserted if the last transaction was not acknowledged by the slave. If an error is not detected and the master has not lost arbitration, the application can proceed with the transfer. The interrupt is cleared by setting the IC bit in the I2C Master Interrupt Clear register (I2C:MICR) to 1.
If the application does not require the use of interrupts, the raw interrupt status is always visible through the I2C Master Raw Interrupt Status register (I2C:MRIS).