Configure a timer to input edge-count mode with the following sequence:
- Ensure the timer is disabled (clear the TAEN bit) before making any changes.
- Write the GPTM Configuration register (GPT:CFG) with a value of 0x0000 0004.
- In the GPTM Timer Mode register (GPT:TnMR), write the TnCMR field to 0x0 and the TnMR field to 0x3.
- Configure the type of events that the timer captures by writing the GPTM Control register (GPT:CTL) TnEVENT field.
- If a prescaler is to be used, write the prescale value to the GPTM Timer n Prescale register (GPT:TnPR).
- Load the timer start value into the GPTM Timer n Interval Load register (GPT:TnILR).
- Load the event count into the GPTM Timer n Match register (GPT:TnMATCHR).
- If interrupts are required, set the GPTM Interrupt Mask register (GPT:IMR) CnMIM bit.
- Set the GPT:CTL TnEN register bit to enable the timer and begin waiting for edge events.
- Poll the GPT:RIS CnMRIS register bit, or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the GPTM Interrupt Clear register (GPT:ICR) CnMCINT bit.
When counting down in input edge-count mode, the timer stops after the programmed number of edge events is detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat Step 4 through Step 9.