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SWCU193A April 2023 – August 2024 CC2340R2 , CC2340R5 , CC2340R5-Q1

1
Read This First
1. About This Manual
2. Devices
3. Register, Field, and Bit Calls
4. Related Documentation
5. Trademarks
1 Architectural Overview
1. 1.1 Target Applications
2. 1.2 Introduction
3. 1.3 Arm Cortex M0+
4. 1.4 On-Chip Memory
5. 1.5 Power Supply System
6. 1.6 Radio
7. 1.7 AES 128-bit Cryptographic Accelerator
8. 1.8 System Timer (SYSTIM)
9. 1.9 General Purpose Timers (LGPT)
10. 1.10 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
11. 1.11 Direct Memory Access
12. 1.12 System Control and Clock
13. 1.13 Communication Peripherals
14. 1.14 Programmable I/Os
15. 1.15 Serial Wire Debug (SWD)
2 Arm Cortex-M0+ Processor
1. 2.1 Introduction
2. 2.2 Block Diagram
3. 2.3 Overview
4. 2.4 Registers
3 Memory Map
1. 3.1 Memory Map
4 Interrupts and Events
1. 4.1 Exception Model
2. 4.2 Fault Handling
  1. 4.2.1 Lockup
3. 4.3 Event Fabric
4. 4.4 Digital Test Bus (DTB)
5. 4.5 EVTULL Registers
6. 4.6 EVTSVT Registers
5 Debug Subsystem
1. 5.1 Introduction
2. 5.2 Block Diagram
3. 5.3 Overview
  1. 5.3.1 Physical Interface
  2. 5.3.2 Debug Access Ports
4. 5.4 Debug Features
5. 5.5 Behavior in Low Power Modes
6. 5.6 Restricting Debug Access
7. 5.7 Mailbox (DSSM)
8. 5.8 Mailbox Events
  1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
9. 5.9 Software Considerations
10. 5.10 DBGSS Registers
6 Power, Reset, and Clocking
1. 6.1 Introduction
2. 6.2 System CPU Modes
3. 6.3 Supply System
  1. 6.3.1 Internal DC/DC Converter and Global LDO
4. 6.4 Power States
5. 6.5 Digital Power Partitioning
6. 6.6 Clocks
  1. 6.6.1 CLKSVT
  2. 6.6.2 CLKULL
7. 6.7 Resets
  1. 6.7.1 Watchdog Timer (WDT)
  2. 6.7.2 LF Loss Detection
8. 6.8 AON (REG3V3) Register Bank
9. 6.9 CKMD Registers
10. 6.10 CLKCTL Registers
11. 6.11 PMCTL Registers
7 Internal Memory
1. 7.1 SRAM
2. 7.2 VIMS
3. 7.3 VIMS Registers
4. 7.4 FLASH Registers
8 Device Boot and Bootloader
1. 8.1 Device Boot and Programming
2. 8.2 Flash Programming
3. 8.3 Device Management Command Interface
  1. 8.3.1 SACI Communication Protocol
  2. 8.3.2 SACI Commands
4. 8.4 Bootloader Support
5. 8.5 ROM Serial Bootloader
9 Device Configuration
1. 9.1 Factory Configuration (FCFG)
2. 9.2 Customer Configuration (CCFG)
10General Purpose Timers (LGPT)
1. 10.1 Overview
2. 10.2 Block Diagram
3. 10.3 Functional Description
4. 10.4 Timer Modes
5. 10.5 LGPT0 Registers
6. 10.6 LGPT1 Registers
7. 10.7 LGPT2 Registers
8. 10.8 LGPT3 Registers
11System Timer (SYSTIM)
1. 11.1 Overview
2. 11.2 Block Diagram
3. 11.3 Functional Description
  1. 11.3.1 Common Channel Features
  2. 11.3.2 Interrupts and Events
4. 11.4 SYSTIM Registers
12Real Time Clock (RTC)
1. 12.1 Introduction
2. 12.2 Block Diagram
3. 12.3 Interrupts and Events
4. 12.4 Capture and Compare Configuration
  1. 12.4.1 Capture
  2. 12.4.2 Compare
5. 12.5 RTC Registers
13Low Power Comparator and SYS0
1. 13.1 Introduction
2. 13.2 Block Diagram
3. 13.3 Functional Description
4. 13.4 SYS0 Registers
14Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
1. 14.1 Introduction
2. 14.2 Functional Description
  1. 14.2.1 BATMON
  2. 14.2.2 DCDC
3. 14.3 PMUD Registers
15Micro Direct Memory Access (µDMA)
1. 15.1 Introduction
2. 15.2 Block Diagram
3. 15.3 Functional Description
4. 15.4 DMA Registers
16Advanced Encryption Standard (AES)
1. 16.1 Introduction
  1. 16.1.1 AES Performance
2. 16.2 Functional Description
3. 16.3 Encryption and Decryption Configuration
4. 16.4 AES Registers
17Analog to Digital Converter (ADC)
1. 17.1 Overview
2. 17.2 Block Diagram
3. 17.3 Functional Description
4. 17.4 Advanced Features
5. 17.5 ADC Registers
18I/O Controller (IOC)
1. 18.1 Introduction
2. 18.2 Block Diagram
3. 18.3 I/O Mapping and Configuration
4. 18.4 Edge Detection
5. 18.5 GPIO
6. 18.6 I/O Pins
7. 18.7 Unused Pins
8. 18.8 Debug Configuration
9. 18.9 IOC Registers
10. 18.10 GPIO Registers
19Universal Asynchronous Receiver/Transmitter (UART)
1. 19.1 Introduction
2. 19.2 Block Diagram
3. 19.3 Functional Description
4. 19.4 Interface to µDMA
5. 19.5 Initialization and Configuration
6. 19.6 UART Registers
20Serial Peripheral Interface (SPI)
1. 20.1 Overview
  1. 20.1.1 Features
  2. 20.1.2 Block Diagram
2. 20.2 Signal Description
3. 20.3 Functional Description
4. 20.4 µDMA Operation
5. 20.5 Initialization and Configuration
6. 20.6 SPI Registers
21Inter-Integrated Circuit (I2C)
1. 21.1 Introduction
2. 21.2 Block Diagram
3. 21.3 Functional Description
4. 21.4 Initialization and Configuration
5. 21.5 I2C Registers
22Radio
1. 22.1 Introduction
2. 22.2 Block Diagram
3. 22.3 Overview
4. 22.4 Radio Usage Model
  1. 22.4.1 CRC and Whitening
5. 22.5 LRFDDBELL Registers
6. 22.6 LRFDRXF Registers
7. 22.7 LRFDTXF Registers
23Revision History

5.3.1 Physical Interface

Debug connections to the device are supported through an Arm serial wire debug (SWD) compliant interface. The SWD interface requires two connections:

A bidirectional data line (SWDIO) used to send data to and receive data from the device
A unidirectional clock line (SWCLK) driven by the debug probe connecting to the device

The SWD interface uses the standard logic levels of the device for SWD communication. See the device-specific data sheet for input and output logic levels for a given supply voltage (VDDS). A SWCLK frequency of up to 10MHz is supported by the DEBUGSS.

During SWD operation, the SWDIO line can be driven high or driven low by either the target device or the debug probe. As either device can drive the line, when ownership of the shared SWDIO line is switched between the device and the debug probe, undriven time slots are inserted as a part of the SWD protocol. The primary purpose of the pullup resistor on the SWDIO line, and the pulldown resistor on the SWCLK line, is to place the SWD pins into a known state when no debug probe is attached. A minimum resistance of 100kΩ is recommended by Arm. The internal pullup/pulldown resistors fulfill this requirement and external resistors are not required for correct operation of the SWD interface.

After a power-on reset (POR), the target device configures the SWD pins in SWD mode with an internal pullup resistor enabled on the SWDIO line and an internal pulldown resistor enabled on the SWCLK line. If the device configuration has not permanently disabled all SWD access, then the SWD interface is enabled during the boot process and a debug probe can be connected to the DEBUGSS.

In the event that a device was configured by software to enter shutdown mode, and a debug probe is then connected to the SWD pins with SWCLK active, wake-up logic triggers an exit from shutdown mode. A debug connection can then be established to the DEBUGSS after the reset sequence completes.

Upon physical connection of a debug probe, a configuration sequence must be sent from the debug probe to the target device to initiate a valid SWD connection with the SW-DP. An invalid sequence doesn't wake the device from shutdown mode. Once the sequence is transmitted and the SWD connection is established, communication with enabled debug access points is possible and the boot code is alerted by asserting the DBGSS.DBGCTL[1] SWDSEL bit, which is continuously monitored in the boot code. The debug probe must be disconnected by sending a disconnection sequence from the debug probe to the target device.

Bootcode can disable the SWD interface in DEBUGSS, freeing the IOs to be used for general-purpose IO functionality. Once the boot code disables SWD functionality, SWD functionality cannot be re-enabled other than by triggering a POR. A POR automatically re-enables the SWD functionality and puts the SWD pins into SWD mode with pullup/pulldown resistors enabled. To regain debug access to a device, hold the device in a reset state with the RSTN pin during a POR. This prevents the boot code from starting and lets the debug probe gain access to the device.