米6体育平台手机版

SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10

Read This First
1. About This Manual
2. Devices
3. Register, Field, and Bit Calls
4. Related Documentation
5. Trademarks
1 Architectural Overview
1. 1.1 Target Applications
2. 1.2 Overview
3. 1.3 Functional Overview
2 Arm Cortex-M33 Processor with FPU
1. 2.1 Arm Cortex-M33 Processor Introduction
2. 2.2 Block Diagram
3. 2.3 Overview
4. 2.4 Programming Model
5. 2.5 Arm® Cortex®-M33 Registers
3 Memory Map
1. 3.1 Introduction
2. 3.2 Memory Map (Secure and Non-secure)
  1. 3.2.1 Bus Security
3. 3.3 Memory Map
4 Arm Cortex-M33 Peripherals
1. 4.1 Arm Cortex-M33 Peripherals Introduction
5 Interrupts and Events
1. 5.1 Exception Model
2. 5.2 Fault Handling
3. 5.3 Security State Switches
4. 5.4 Event Fabric
  1. 5.4.1 Introduction
  2. 5.4.2 Event Fabric Overview
    1. 5.4.2.1 Registers
5. 5.5 AON Event Fabric
  1. 5.5.1 Common Input Event List
  2. 5.5.2 Event Subscribers
6. 5.6 MCU Event Fabric
  1. 5.6.1 Common Input Event List
  2. 5.6.2 Event Subscribers
7. 5.7 AON Events
8. 5.8 Interrupts and Events Registers
  1. 5.8.1 AON_EVENT Registers
  2. 5.8.2 EVENT Registers
6 JTAG Interface
1. 6.1 Overview
2. 6.2 cJTAG
3. 6.3 ICEPick
4. 6.4 ICEMelter
5. 6.5 Serial Wire Viewer (SWV)
6. 6.6 Halt In Boot (HIB)
7. 6.7 Debug and Shutdown
8. 6.8 Boundary Scan
7 Power, Reset, and Clock Management (PRCM)
1. 7.1 Introduction
2. 7.2 System CPU Mode
3. 7.3 Supply System
  1. 7.3.1 Internal DC/DC Converter and Global LDO
  2. 7.3.2 External Regulator Mode
4. 7.4 Digital Power Partitioning
  1. 7.4.1 MCU_VD
    1. 7.4.1.1 MCU_VD Power Domains
  2. 7.4.2 AON_VD
    1. 7.4.2.1 AON_VD Power Domains
5. 7.5 Clock Management
6. 7.6 Power Modes
7. 7.7 Reset
8. 7.8 PRCM Registers
8 Versatile Instruction Memory System (VIMS)
1. 8.1 Introduction
2. 8.2 VIMS Configurations
3. 8.3 VIMS Software Remarks
  1. 8.3.1 FLASH Program or Update
  2. 8.3.2 VIMS Retention
4. 8.4 FLASH
  1. 8.4.1 Flash Memory Protection
  2. 8.4.2 Flash Memory Programming
5. 8.5 ROM Functions
6. 8.6 VIMS Registers
9 SRAM
1. 9.1 Introduction
2. 9.2 Main Features
3. 9.3 Data Retention
4. 9.4 Parity and SRAM Error Support
  1. 9.4.1 SRAM Extension Mode
5. 9.5 SRAM Auto-Initialization
6. 9.6 Parity Debug Behavior
7. 9.7 SRAM Registers
  1. 9.7.1 SRAM_MMR Registers
  2. 9.7.2 SRAM Registers
10Bootloader
1. 10.1 Bootloader Functionality
  1. 10.1.1 Bootloader Disabling
  2. 10.1.2 Bootloader Backdoor
2. 10.2 Bootloader Interfaces
11Device Configuration
1. 11.1 Customer Configuration (CCFG)
  1. 11.1.1 CCFG Recommendations for Final Production
2. 11.2 CCFG Registers
3. 11.3 Factory Configuration (FCFG)
4. 11.4 FCFG1 Registers
12AES and Hash Cryptoprocessor
1. 12.1 Introduction
2. 12.2 Functional Description
3. 12.3 DMA Controller
  1. 12.3.1 Internal Operation
  2. 12.3.2 Supported DMA Operations
4. 12.4 AES and Hash Cryptoprocessor Performance
  1. 12.4.1 Introduction
  2. 12.4.2 Performance for DMA-Based Operations
5. 12.5 Programming Guidelines
6. 12.6 Conventions and Compliances
  1. 12.6.1 Conventions Used in This Manual
    1. 12.6.1.1 Terminology
    2. 12.6.1.2 Formulas and Nomenclature
  2. 12.6.2 Compliance
7. 12.7 CRYPTO Registers
13PKA Engine
1. 13.1 Introduction
2. 13.2 Functional Description
3. 13.3 PKA Engine Performance
4. 13.4 PKA Registers
14True Random Number Generator (TRNG)
1. 14.1 Introduction
2. 14.2 Block Diagram
3. 14.3 TRNG Software Reset
4. 14.4 Interrupt Requests
5. 14.5 TRNG Operation Description
6. 14.6 TRNG Low-Level Programming Guide
  1. 14.6.1 Initialization
7. 14.7 TRNG Registers
15I/O Controller (IOC)
1. 15.1 Introduction
2. 15.2 IOC Overview
3. 15.3 I/O Mapping and Configuration
4. 15.4 Edge Detection on DIO Pins
  1. 15.4.1 Configure DIO as GPIO Input to Generate Interrupt on Edge Detect
5. 15.5 Unused I/O Pins
6. 15.6 GPIO
7. 15.7 I/O Pin Capability
8. 15.8 Peripheral PORT_IDs
9. 15.9 I/O Pins
  1. 15.9.1 Input/Output Modes
    1. 15.9.1.1 Physical Pin
    2. 15.9.1.2 Pin Configuration
10. 15.10 IOC Registers
16Micro Direct Memory Access (µDMA)
1. 16.1 Introduction
2. 16.2 Block Diagram
3. 16.3 Functional Description
4. 16.4 Initialization and Configuration
  1. 16.4.1 Module Initialization
  2. 16.4.2 Configuring a Memory-to-Memory Transfer
5. 16.5 UDMA Registers
17Timers
1. 17.1 Introduction
2. 17.2 Block Diagram
3. 17.3 Functional Description
4. 17.4 Initialization and Configuration
5. 17.5 GPT Registers
18Real-Time Clock (RTC)
1. 18.1 Introduction
2. 18.2 Functional Specifications
3. 18.3 RTC Register Information
4. 18.4 RTC Registers
  1. 18.4.1 AON_RTC Registers
19Watchdog Timer (WDT)
1. 19.1 Introduction
2. 19.2 Functional Description
3. 19.3 Initialization and Configuration
4. 19.4 WDT Registers
20AUX Domain Sensor Controller and Peripherals
1. 20.1 Introduction
  1. 20.1.1 AUX Block Diagram
2. 20.2 Power and Clock Management
3. 20.3 Sensor Controller
  1. 20.3.1 Sensor Controller Studio
  2. 20.3.2 Sensor Controller Engine (SCE)
4. 20.4 Digital Peripheral Modules
5. 20.5 Analog Peripheral Modules
6. 20.6 Event Routing and Usage
7. 20.7 Sensor Controller Alias Register Space
8. 20.8 AUX Domain Sensor Controller and Peripherals Registers
21Battery Monitor and Temperature Sensor (BATMON)
1. 21.1 Introduction
2. 21.2 Functional Description
3. 21.3 AON_BATMON Registers
22Universal Asynchronous Receiver/Transmitter (UART)
1. 22.1 Introduction
2. 22.2 Block Diagram
3. 22.3 Signal Description
4. 22.4 Functional Description
5. 22.5 Interface to µDMA
6. 22.6 Initialization and Configuration
7. 22.7 UART Registers
23Serial Peripheral Interface (SPI)
1. 23.1 Introduction
2. 23.2 Block Diagram
3. 23.3 Signal Description
4. 23.4 Functional Description
5. 23.5 μDMA Operation
6. 23.6 Initialization and Configuration
7. 23.7 SPI Registers
24Inter-Integrated Circuit (I2C)
1. 24.1 Introduction
2. 24.2 Block Diagram
3. 24.3 Functional Description
4. 24.4 Initialization and Configuration
5. 24.5 I2C Registers
25Inter-IC Sound (I2S)
1. 25.1 Introduction
2. 25.2 Block Diagram
3. 25.3 Signal Description
4. 25.4 Functional Description
5. 25.5 Memory Interface
6. 25.6 Samplestamp Generator
7. 25.7 Error Detection
8. 25.8 Usage
  1. 25.8.1 Start-Up Sequence
  2. 25.8.2 Shutdown Sequence
9. 25.9 I2S Registers
26Radio
1. 26.1 RF Core
  1. 26.1.1 High-Level Description and Overview
2. 26.2 Radio Doorbell
3. 26.3 RF Core HAL
4. 26.4 Data Queue Usage
  1. 26.4.1 Operations on Data Queues Available Only for Internal Radio CPU Operations
  2. 26.4.2 Radio CPU Usage Model
    1. 26.4.2.1 Receive Queues
    2. 26.4.2.2 Transmit Queues
5. 26.5 IEEE 802.15.4
6. 26.6 Bluetooth® Low Energy
  1. 26.6.1 Bluetooth® Low Energy Commands
  2. 26.6.2 Interrupts
7. 26.7 Data Handling
  1. 26.7.1 Receive Buffers
  2. 26.7.2 Transmit Buffers
8. 26.8 Radio Operation Command Descriptions
9. 26.9 Immediate Commands
  1. 26.9.1 Update Advertising Payload Command
10. 26.10 Proprietary Radio
11. 26.11 Radio Registers
27Revision History

26.3.2.5.1 Triggers

Triggers can be used to set up a start time, or for other specific purposes in specific radio operation commands. A common trigger byte definition exists, as defined in Table 26-4.

Table 26-4 Format of Trigger Definition Byte

Bit Index	Field	Description
0–3	triggerType	The type of trigger
4	bEnaCmd	0: No alternative trigger command. 1: CMD_TRIGGER can be used as an alternative trigger.
5–6	triggerNo	The trigger number of the CMD_TRIGGER command that triggers this action.
7	pastTrig	0: A trigger in the past is never triggered, or for start of commands, give an error. 1: A trigger in the past is triggered as soon as possible.

The triggerType can take the values listed in Table 26-5. Other values are reserved.

Table 26-5 Supported Trigger Types

Number	Name	Description
0	TRIG_NOW	Now (not applicable to end triggers)
1	TRIG_NEVER	Never (except possibly by CMD_TRIGGER if bEnaCmd = 1)
2	TRIG_ABSTIME	At absolute time, given by timer parameter
3	TRIG_REL_SUBMIT	At a time relative to the time the command was submitted
4	TRIG_REL_START	At a time relative to start of this command (not allowed for start triggers)
5	TRIG_REL_PREVSTART	At a time relative to the start of the previous command
6	TRIG_REL_FIRSTSTART	At a time relative to the start of the first command of the chain
7	TRIG_REL_PREVEND	At a time relative to the end of the previous command
8	TRIG_REL_EVT1	At a time relative to event 1 of the previous command
9	TRIG_REL_EVT2	At a time relative to event 2 of the previous command
10	TRIG_EXTERNAL	On an external trigger input to the RAT

A 32-bit time parameter is used together with all triggers except for TRIG_NOW and TRIG_NEVER. Absolute timing uses the value of the 32-bit RAT. Relative timing uses the number of RAT ticks. The external trigger uses an identifier of source and edge, as defined in Table 26-6.

Table 26-6 Fields of Time Parameter for External Event Trigger

Bit Index	Field	Description
0–1		Reserved
2–3	inputMode	Input mode 00: Rising edge 01: Falling edge 10: Both edges 11: Reserved
4–7		Reserved
8–12	source	22: RFC_GPI0 23: RFC_GPI1 Others: Reserved
13–31		Reserved

Relative timing can either be relative to the time of submitting the command chain, to the start of the command, to the start of the previous or first command, or to certain observed events inside the command, to be defined for each command. The following rules apply:

For the first command in a chain, if the start trigger is any of the types 5 through 9, the start is immediate. If another trigger referenced in the first command in a chain is any of the types 5 through 9, the trigger time is relative to the time the command was submitted.
If the start trigger of a command is TRIG_REL_START, an error is produced.
If the start trigger of a command is TRIG_NEVER and bEnaCmd is 0, an error is produced.
Some radio operation commands define events 1 and 2. These are context-dependent events that can be observed by the radio CPU. See the description of each command for a definition in that context. If undefined, these events are the time of the start of the command.

If bEnaCmd is 1, the action may also be triggered with a command (CMD_TRIGGER command, see Section 26.3.3.2.5). The triggerNo parameter identifies the trigger number of this command.

If a trigger occurs in the past when evaluated, the behavior depends on the pastTrig bit. If this bit is 0, the trigger does not occur, or for start triggers, an error is produced. If this bit is 1, the trigger occurs as soon as possible. If the pastTrig bit is 1 for start triggers, timing relative to the start of the command is relative to the programmed start time, not the actual start time.

For an external trigger, the radio CPU sets the RAT to use the selected input event as a one-capture trigger; the CPU then uses this capture interrupt to trigger the action. If the event occurs before the setup occurs, the event is not captured, and the pastTrig bit is ignored.